Redistribution Substrate Line Profile for Compact Reliable Chip Packaging
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving compact size and improved reliability and durability, particularly in connecting semiconductor chips to printed circuit boards efficiently.
Innovation Solution
The development of a semiconductor package with a redistribution substrate featuring redistribution line patterns in a dielectric layer, including planar top surfaces and non-planar bottom surfaces, and via parts that penetrate the dielectric layer, along with a method of fabricating these patterns using anisotropic etching processes to create convex and rounded edges, enhancing connectivity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding methods are used to connect semiconductor chips to PCBs, then electrical connections can be established, but the package size increases and reliability is limited
Solution Approach 1:
The patent transitions from planar 2D wiring patterns to 3D vertical interconnections through via holes that penetrate through substrate layers. The via holes create vertical electrical pathways, enabling compact redistribution of signal paths in the thickness direction, thus reducing the overall package footprint while maintaining connection reliability
Solution Approach 2:
The patent implements nested structures where via holes are embedded within substrate layers, and redistribution patterns are layered in multiple dielectric levels. The via holes are surrounded by barrier layers and filled with conductive materials, creating concentric nested structures that maximize space utilization and enable compact packaging
2Manufacturing precision
If standard redistribution patterns are used, then electrical connections are established, but manufacturing precision and pattern fidelity deteriorate
Solution Approach 1:
The patent performs preliminary planarization of the substrate surface before forming via holes and depositing conductive patterns. This preliminary flattening action ensures that subsequent lithography and etching processes can achieve high pattern precision, while the planarized surface also simplifies the overall fabrication流程 by providing a uniform baseline for subsequent steps
3Temperature
If thermal management structures are added to the package, then thermal radiation improves, but device complexity increases
Solution Approach 1:
The patent integrates thermal management functions into existing package substrates and interconnection structures. The same substrate layers and via hole structures that provide electrical connections also serve as thermal conduction pathways, eliminating the need for separate dedicated thermal management components and maintaining device simplicity while improving heat dissipation
Data Source
AI summary
Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.