Redistribution Line Structures on Chip Side Surfaces
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Solution Overview
Problem
Current semiconductor package technologies face challenges in achieving high density and performance while maintaining a small form factor, particularly in the efficient electrical interconnection of vertically stacked semiconductor chips.
Innovation Solution
The implementation of redistribution line structures on both surfaces and side surfaces of semiconductor chips, allowing for electrical connections between chips without the need for through-silicon vias (TSVs), enabling efficient electrical paths for vertically stacked sub-stack structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked semiconductor chips are used to achieve high density and small form factor, then packaging density and performance are improved, but electrical interconnection complexity increases
Solution Approach 1:
The patent extends redistribution line structures from traditional planar surfaces onto the side surfaces of semiconductor chips. This three-dimensional routing approach allows electrical connections to utilize the vertical dimension, reducing the complexity of interconnections in vertically stacked packages while maintaining high packaging density.
Solution Approach 2:
The electrical interconnection system is divided into multiple redistribution line structures distributed across different surfaces (top, bottom, and side surfaces) of the chips. This segmentation allows the complex interconnection task to be distributed across multiple simpler routing paths, reducing overall system complexity.
2Productivity
If redistribution line structures are extended onto side surfaces of chips, then electrical interconnection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent integrates the redistribution line structures onto the side surfaces of chips during the existing semiconductor manufacturing process, rather than adding a separate post-processing step. This merging of functions allows the same manufacturing infrastructure to produce both planar and three-dimensional routed connections, reducing manufacturing complexity while improving interconnection efficiency.
3Reliability
If through-silicon vias (TSVs) are used for vertical electrical connections, then electrical interconnection is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the electrical interconnection function from the traditional through-silicon via approach and implements it through redistribution line structures on chip surfaces and side surfaces. This extraction eliminates the need for complex TSV fabrication processes while maintaining reliable electrical connections between stacked chips.
Data Source
AI summary
A chip stack package includes first and second semiconductor chips. A first redistribution line structure is disposed on a front surface of the first semiconductor chip, and the first redistribution line structure extends onto a side surface of the first semiconductor chip. A second redistribution line structure is disposed on the front surface of the first semiconductor chip, and the second redistribution line structure extends onto the side surface of the first semiconductor chip. A third redistribution line structure is disposed on a front surface of the second semiconductor chip, and the third redistribution line structure extends onto a side surface of the second semiconductor chip to be electrically connected to the second redistribution line structure.