Redistribution Lines for Stacked Chip Wirebonding
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Solution Overview
Problem
In stacked chip packages, the length of wirebonding wires is often excessive due to pad position differences between semiconductor chips, leading to compromised electrical performance and the need for redesigning circuit layouts to expose chip pads, which increases production costs.
Innovation Solution
The use of redistribution lines on the semiconductor chips to change the pad positions, allowing for shorter wirebonding wires and avoiding pad blockage by the substrate, without requiring redesign of the circuit layout under the passivation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is performed directly from chip pads to substrate pads, then the connection is simple, but the wire length becomes excessive when pad positions differ, compromising electrical performance
Solution Approach 1:
The patent introduces an intermediary structure (redistribution lines or additional pads) between the chip pads and substrate pads. This intermediary allows the wire bonding path to be optimized, reducing wire length while maintaining electrical connection. The redistribution lines act as a mediator that redirects the wire path to achieve shorter connections.
Solution Approach 2:
The patent utilizes the third dimension (vertical stacking) to reduce wire length. By stacking chips vertically and using through-substrate vias or redistribution layers, the wire bonding path is shortened from a long horizontal path to a shorter path that utilizes the vertical dimension, thereby reducing overall wire length and improving electrical performance.
2Ease of manufacture
If chip pads are repositioned to avoid substrate blockage, then wire bonding becomes feasible, but the circuit layout under the passivation layer must be redesigned, increasing production costs
Solution Approach 1:
The patent segments the pad structure into multiple layers: original chip pads remain in their fixed positions under the passivation layer, while new redistribution pads are created at different locations. This segmentation allows the original circuit layout to remain unchanged while new pads are added separately to enable wire bonding, avoiding the need to redesign the entire circuit layout.
Solution Approach 2:
The patent introduces redistribution lines as intermediary conductors that connect the original chip pads (which remain in their fixed positions) to new pad locations that are accessible for wire bonding. This intermediary structure allows wire bonding to proceed without moving the original pads or redesigning the underlying circuit layout, thus maintaining manufacturing feasibility while enabling wire bonding.
3Area of stationary object
If multiple chips are stacked to increase integration density, then package size is reduced, but pad position mismatches between chips cause excessive wire lengths
Solution Approach 1:
The patent creates a universal pad structure that can accommodate multiple stacked chips with different pad positions. The redistribution lines and additional pads are designed to work with various chip configurations, allowing the same package structure to handle pad position mismatches across different chips in the stack, thereby reducing wire lengths for all chips simultaneously while maintaining compact packaging.
Data Source
AI summary
A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.