Redistribution Structure Shielding for Low-Loss Semiconductor Packaging
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Solution Overview
Problem
The challenge of integrating multiple semiconductor devices in miniaturized electronic apparatus while ensuring lower transmission and insertion losses and improving electrical performance has not been adequately addressed by existing packaging and assembling techniques.
Innovation Solution
A semiconductor package with a redistribution structure that includes a carrier, redistribution layers, through insulator vias, semiconductor dies, and connective terminals, which are encapsulated and connected through a series of metallization tiers and dielectric layers, allowing for efficient electrical connections and stress management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor devices are integrated in miniaturized electronic apparatus using existing packaging techniques, then device integration density increases, but transmission loss and insertion loss increase while electrical performance deteriorates
Solution Approach 1:
The patent transitions from planar wafer-level packaging to three-dimensional stacked packaging architecture. Multiple semiconductor devices are vertically stacked and interconnected through through-silicon vias (TSVs) and redistribution layers, enabling high-density integration while maintaining short signal paths that reduce transmission loss and preserve electrical performance.
Solution Approach 2:
The patent implements nested interconnection structures where redistribution layers are embedded within dielectric layers, which are in turn enclosed by protective encapsulants. This nested architecture allows multiple interconnection levels to be compactly integrated, achieving high device density without compromising signal integrity or increasing transmission loss.
2Productivity
If semiconductor devices are packaged at wafer level with existing techniques, then manufacturing efficiency improves, but mechanical stress and delamination occur reducing package reliability
Solution Approach 1:
The patent modifies the packaging process parameters by implementing a multi-stage approach: initial wafer-level bonding followed by singulation, then individual die stacking and reflow processing. This parameter optimization allows efficient manufacturing while controlling thermal and mechanical stress through controlled reflow temperature profiles, preventing delamination and improving package reliability.
Solution Approach 2:
The patent employs stress compensation structures including compliant underfills and flexible dielectric layers that are pre-installed to absorb and distribute mechanical stress during subsequent packaging and operation. These cushioning elements prevent stress concentration that would otherwise cause delamination, maintaining package reliability through the manufacturing process.
3Volume of moving object
If miniaturization is pursued to meet increasing demand, then device size decreases, but transmission loss increases and electrical performance deteriorates
Solution Approach 1:
The patent uses vertical stacking to reduce the horizontal footprint while maintaining functional performance. By moving interconnections to the vertical dimension through TSVs and multiple redistribution layers, the device achieves miniaturization without lengthening signal paths, thereby preventing increased transmission loss that would normally accompany size reduction.
Solution Approach 2:
The patent nests multiple interconnection levels within compact vertical structures, embedding redistribution layers within dielectric layers. This nested configuration allows the device to be miniaturized while keeping interconnection paths short and direct, minimizing signal loss and maintaining electrical performance despite reduced device volume.
Data Source
AI summary
A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.