Redistribution Structure Layout for CTE-Stress-Resistant Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in creating smaller and more reliable packaging techniques for semiconductor dies due to thermal expansion mismatch, leading to stress and deformation in metallization patterns, which can compromise the integrity and reliability of semiconductor packages.
Innovation Solution
The implementation of flexibly-shaped metallization patterns, surrounded by conforming dielectric layers, with specific via and pad arrangements, and stacked vias to mitigate stress caused by coefficient of thermal expansion (CTE) mismatch, enhancing the reliability of redistribution and under-bump metallization structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor packages use conventional rigid metallization patterns, then manufacturing is simpler, but thermal expansion mismatch causes stress and deformation compromising reliability
Solution Approach 1:
The metallization pattern transitions from a rigid conventional design to a dynamic flexible design that can adapt its shape. The pattern includes curved sections and variable width regions that allow the metallization to flex and deform elastically in response to thermal expansion forces, preventing stress concentration and connection failure while maintaining electrical connectivity.
Solution Approach 2:
The metallization pattern is designed as a flexible thin film structure rather than a rigid bulk material. By creating thin metal traces with controlled geometry including curved paths and width variations, the metallization layer gains flexibility to accommodate thermal expansion mismatch between different package components without breaking or delaminating.
2Stress or pressure
If metallization patterns are made flexible to accommodate thermal expansion, then stress is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The metallization pattern is segmented into distinct functional zones including straight connection sections, curved transition sections, and width-modulation sections. Each segment serves a specific purpose: straight sections provide low-resistance current paths, curved sections provide flexibility and stress relief, and width variations provide gradual transition zones. This segmentation allows standard manufacturing processes to produce each segment with adequate precision while the overall pattern achieves stress management.
Solution Approach 2:
The metallization pattern utilizes controlled changes in geometric parameters including trace width, curvature radius, and path length. These parameter variations are designed within tolerances achievable by conventional PCB and semiconductor manufacturing processes. The width transitions and curvature radii are optimized to provide sufficient flexibility while maintaining manufacturability with standard equipment and process capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described structures improve the reliability of semiconductor packages by effectively managing stress and deformation, ensuring the integrity and functionality of semiconductor devices under varying thermal conditions.
Implementation Method 1
with flexibly-shaped metallization patterns, surrounded by conforming dielectric layers, with specific via and pad arrangements, and stacked vias to mitigate stress caused by coefficient of thermal expansion (CTE) mismatch
Data Source
AI summary
A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.