Redistribution-Layer Substrate Structure for 3DIC Verification

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Solution Overview

Problem

Existing methods and apparatus for testing integrated circuit (IC) devices are not entirely satisfactory in ensuring effective functionality and reliability, particularly in the context of smaller and more complex IC devices.

Innovation Solution

A substrate structure is developed with a debond layer, conductive patterns, redistribution layers, and conductive pads, allowing for efficient electrical examination and verification testing of 3D packaging or 3DIC devices, incorporating test pads and probe cards for intermediate and final structure verification, and utilizing materials like benzocyclobutene and polybenzoxazole for dielectric layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing testing methods are used for smaller and more complex IC devices, then the testing process can be completed, but the functionality and reliability verification becomes insufficient

Engineering Contradiction:
Improvefunctionality and reliability verificationVSAvoidcomplexity of IC devices
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The substrate structure is divided into multiple functional layers including debond layer, dielectric layers, conductive patterns, and test pads. This segmentation allows independent verification of different device regions and enables comprehensive testing of complex IC devices through modular test structures

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Test pads and conductive patterns are pre-formed on the substrate before the IC device is fully assembled. This preliminary action enables early verification testing of known good dies and allows testing to be performed at intermediate stages of device fabrication, ensuring reliability before final assembly

Inventive Principle:
Principle #10Preliminary action

2Productivity

If comprehensive verification testing is performed on known good dies, then yield and reliability are improved, but the testing time and process complexity increase

Engineering Contradiction:
ImproveyieldVSAvoidtesting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Verification testing is performed at multiple intermediate stages rather than only at the final stage. Known good dies are identified and verified early in the process using pre-formed test pads, reducing the need for extensive final testing and improving overall yield while managing testing time

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The substrate structure with its debond layer, dielectric layers, and conductive patterns serves as an intermediary testing platform. This mediator enables efficient electrical examination of IC devices without requiring complex final test setups, reducing testing time while maintaining comprehensive verification

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250298056A1Substrate structure
Publication Date: 2025.09.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250298056A1 patent drawing
  • US20250298056A1 patent drawing
  • US20250298056A1 patent drawing

AI summary

A substrate structure includes a core substrate, a redistribution layer, a plurality of test pads, a first protective coating, at least one conductive pad and a passive device. The redistribution layer is disposed on and electrically connected to the core substrate. The test pads are disposed over the redistribution layer. The first protective coating is coated on the test pads. The conductive pad is d disposed on the redistribution layer aside the plurality of test pads. The passive device is disposed on and electrically connected to the at least one conductive pad.