Redistribution Via Planarization for Tighter Bond Pad Pitch
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Solution Overview
Problem
Conventional semiconductor packaging techniques face challenges in achieving a reduced minimum pitch between bond vias and bond pads due to the non-flat surface of redistribution vias, limiting the integration density and efficiency of semiconductor devices.
Innovation Solution
The formation of redistribution vias and pads with a flat or level top surface through processes like single or dual damascene, followed by planarization, allows for direct overlap of bond vias and pads, reducing the minimum pitch by at least 35%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional packaging techniques are used with non-flat redistribution via surfaces, then the manufacturing process is simpler, but the minimum pitch between bond vias and bond pads cannot be reduced
Solution Approach 1:
The patent applies preliminary action by performing planarization of the redistribution via surface before forming the bond pads. This advance preparation creates a flat surface that enables subsequent direct overlap of bond vias and pads, achieving reduced minimum pitch. The planarization step is executed in advance to eliminate surface irregularities that would otherwise prevent tight spacing.
Solution Approach 2:
The patent transitions from a two-dimensional layout approach to a three-dimensional stacked approach. By forming bond vias and pads in vertical stacks that overlap in the planar dimension, the design utilizes the vertical dimension to achieve reduced pitch. The planarization enables this vertical stacking by providing a flat reference surface for precise alignment.
2Productivity
If redistribution vias are formed with flat top surfaces through planarization, then integration density is enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The planarization process is performed as a preliminary action before bond pad formation. This advance flattening of the redistribution via surface enables the subsequent direct overlap configuration, achieving higher integration density. The preliminary planarization eliminates the need for offset configurations that would reduce density.
Solution Approach 2:
The patent changes the surface topology parameter of the redistribution via from non-flat to flat through planarization. This parameter change enables the bond vias and pads to be formed with direct overlap, increasing the number of interconnections per unit area and thereby enhancing integration density.
Data Source
AI summary
An embodiment is a method including forming a first interconnect structure over a first substrate, forming a redistribution via over the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure, forming a redistribution pad over the redistribution via, the redistribution pad being electrically coupled to the redistribution via, forming a first dielectric layer over the redistribution pad, and forming a second dielectric layer over the first dielectric layer. The method also includes patterning the first and second dielectric layers, forming a bond via over the redistribution pad and in the first dielectric layer, the bonding via being electrically coupled to the redistribution pad, the bond via overlapping the redistribution via, and forming a first bond pad over the bonding via and in the second dielectric layer, the first bond pad being electrically coupled to the bond via.