Redistribution Via Hole Structure for Better Step Coverage
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Solution Overview
Problem
The increasing demand for high-functionality and miniaturization in semiconductor devices leads to reduced via widths, resulting in deteriorated step coverage and increased resistance, along with the occurrence of overhang phenomena in redistribution layers, which can cause failures in semiconductor devices.
Innovation Solution
A semiconductor device with a redistribution conductive layer featuring a via hole structure having multiple slopes, where the second slope is less than the first slope, and a manufacturing method using a mask pattern with parasitic patterns to enhance step coverage without additional processing steps, thereby improving contact area and preventing overhangs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the via width is reduced to achieve miniaturization and high integration, then the device can achieve higher functionality and smaller size, but the step coverage deteriorates and resistance increases
Solution Approach 1:
The via hole structure is segmented into multiple slopes (first slope and second slope) rather than a single uniform slope. This segmentation allows each slope to be optimized independently - the first slope provides adequate step coverage while the second slope maintains the via width for low resistance, resolving the contradiction between miniaturization and manufacturing precision
Solution Approach 2:
Different regions of the via hole are assigned different slope characteristics. The first slope region is designed with a specific angle to ensure proper step coverage of the redistribution layer, while the second slope region is designed with a different angle to maintain via width and reduce resistance. This local differentiation allows simultaneous optimization of both step coverage and electrical performance in high integration scenarios
2Productivity
If the via width is reduced to achieve miniaturization, then the device can achieve higher integration level, but the resistance of the redistribution conductive layer increases
Solution Approach 1:
The via hole is divided into multiple slope sections that allow the via width to be maintained at an optimal level despite the overall miniaturization trend. This segmentation enables the redistribution conductive layer to have sufficient contact area with the underlying conductive layer, thereby maintaining low resistance even as the device achieves higher integration levels
Solution Approach 2:
The slope angles of the via hole walls are changed and optimized - the first slope has a different angle than the second slope. By adjusting these geometric parameters, the via structure can maintain adequate width for low resistance while still achieving the required miniaturization for high integration, thus improving both productivity and reliability
3Ease of manufacture
If a conventional via hole structure is used, then the manufacturing process is simpler, but the redistribution layer exhibits overhang phenomenon causing device failures
Solution Approach 1:
The via hole structure is segmented into multiple slopes that can be formed using a single etching process with a specifically designed mask pattern. This segmentation prevents the overhang phenomenon by ensuring each slope portion is properly supported, thereby improving reliability without significantly complicating the manufacturing process
Solution Approach 2:
The mask pattern is designed in advance with parasitic patterns that pre-determine the multi-slope structure of the via hole. This preliminary design of the mask pattern ensures that the via hole will have the optimal multi-slope geometry to prevent overhangs, thereby improving device reliability while maintaining ease of manufacture through a standard photolithography process
Data Source
AI summary
A semiconductor device includes a substrate. A conductive layer is disposed on the substrate and extends in a first direction. An insulating layer is disposed on the conductive layer and exposes at least a portion of the conductive layer through a via hole. The via hole includes a first face extending in a first slope relative to a top face of the conductive layer. A second face extends in a second slope relative to the top face of the conductive layer that is less than the first slope. A redistribution conductive layer includes a first pad area disposed in the via hole. A line area at least partially extends along the first face and the second face. The first face directly contacts the conductive layer. The second face is positioned at a higher level than the first face in a second direction perpendicular to a top face of the substrate.