Reduced Pin JTAG Interface Maintains Bandwidth

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Solution Overview

Problem

Modern ICs face challenges in reducing the number of JTAG pins while maintaining high communication bandwidth for test, emulation, debug, and trace operations, especially with the trend towards smaller IC packaging in mobile applications.

Innovation Solution

A reduced pin interface for JTAG-based transactions between a JTAG controller and a target IC, utilizing a 2-signal JTAG bus that maintains half the data communication bandwidth of a full JTAG interface, allowing operations at half the frequency of standard 5-pin JTAG interfaces, thereby enabling three times the bandwidth of existing approaches like the J-Link system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of JTAG pins is reduced, then more pins are available for functional purposes, but the communication bandwidth for test operations decreases

Engineering Contradiction:

Improvenumber of available pinsVSAvoidcommunication bandwidth

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent implements a 2-signal interface that transmits JTAG data periodically by alternating between input and output phases synchronized to a clock signal. This periodic action allows the reduced pin interface to maintain effective communication bandwidth by efficiently utilizing the available signals over time, achieving three times the bandwidth of existing reduced pin approaches like J-Link.

Inventive Principle:

Principle #19Periodic action

2Quantity of substance

If a 2-signal JTAG bus is used, then the pin count is reduced, but the operating frequency must be halved to maintain half the data communication bandwidth

Engineering Contradiction:

Improvepin countVSAvoidoperating frequency

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The patent changes the operational parameters by implementing a phased transmission mode where data is transmitted in alternating input/output phases rather than simultaneously. This parameter change allows the system to operate at reduced frequency while maintaining acceptable bandwidth through efficient time-division multiplexing of the two signals.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If dedicated JTAG pins are used, then reliable test operations are ensured, but the number of functional pins is reduced

Engineering Contradiction:

Improvetest operation reliabilityVSAvoidnumber of functional pins

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent implements a universal interface where the same two pins used for JTAG operations can also serve functional purposes when not engaged in test mode. The controller can selectively configure the pins for JTAG input/output operations or leave them floating for functional use, allowing the system to maintain reliability when needed while maximizing pin availability for functional applications.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8880966B2Transitioning POLL IN to set MRST and CE high states

Publication Date: 2014.11.04 TEXAS INSTRUMENTS INC

AI summary

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.