Reduced SDF File Generation for Gate Level Simulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of integrated circuit designs results in larger Standard Delay Format (SDF) files, which burden gate level simulators with longer runtimes and larger memory requirements, necessitating a reduction in simulator run time and memory usage.
Innovation Solution
A method and system for generating reduced SDF files by marking internal register to register data paths as zero delay and applying delay adjustments to endpoints with hold time violations, while ensuring these adjustments do not cause setup time violations, thereby reducing the size of SDF files and simulator requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full chip SDF files containing delays for all timing arcs are used for gate level simulation, then timing analysis accuracy is improved, but simulator runtime and memory requirements increase
Solution Approach 1:
The patent extracts only the essential timing information needed for simulation by identifying and removing zero-delay internal paths from the full SDF file. This extraction process creates a reduced SDF file that contains only the timing arcs that actually affect simulation results, thereby reducing simulator runtime while preserving timing analysis accuracy for the relevant signals.
Solution Approach 2:
The patent segments the timing arcs into two categories: those that require simulation (non-zero delay paths affecting output pins) and those that do not (zero-delay internal paths). By segmenting the SDF file in this way, the simulation tool can focus computational resources only on the necessary timing arcs, reducing overall runtime while maintaining accuracy where it matters.
2Measurement precision
If full chip SDF files containing delays for all timing arcs are used for gate level simulation, then timing analysis accuracy is improved, but memory requirements increase
Solution Approach 1:
The patent extracts and removes unnecessary timing arc data from the SDF file, keeping only the essential timing information. This reduces the quantity of data that must be loaded into simulator memory while preserving the timing accuracy needed for valid simulation results.
Solution Approach 2:
By segmenting timing arcs into essential and non-essential categories, the patent reduces the memory footprint of the SDF file by excluding zero-delay internal paths that do not contribute to simulation accuracy, thereby lowering memory requirements.
3Loss of time
If internal register to register data paths are marked as zero delay to reduce SDF file size, then simulator runtime and memory requirements are reduced, but hold time violations may occur
Solution Approach 1:
The patent applies local quality by differentiating between internal paths (which can be marked zero delay) and output paths (which must retain their actual delays). This localized approach allows the patent to reduce SDF file size and simulator runtime while preserving timing constraint compliance for signals that actually affect simulation results.
Solution Approach 2:
The patent changes the delay parameter for specific internal register-to-register paths, setting them to zero delay, while maintaining actual delay values for paths that affect output pins. This selective parameter change reduces overall SDF size and simulation complexity while preserving timing reliability where it matters.
Data Source
AI summary
A system and method for generating standard delay format (SDF) files is disclosed. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.