Triple-Voting Redundancy Circuit With Selective Scan-Enable Control
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Solution Overview
Problem
Achieving 100% at-speed and stuck-at fault coverage in triple-voting flops during scan testing is challenging, especially in detecting slow-to-rise and slow-to-fall faults, as existing methods like LOC and LOS testing may mask such faults.
Innovation Solution
Implementing a triple-voting flop with additional scan flip-flops and a scan enable control circuit that selectively controls the scan enable inputs, allowing independent value loading and improved scan coverage by using LOC testing, which enables easier implementation and flexibility in scan circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If LOC testing is used to achieve easier implementation and flexibility in scan circuit design, then device complexity is reduced, but measurement precision of slow-to-rise and slow-to-fall faults deteriorates
Solution Approach 1:
The scan chain is segmented into multiple independent scan chains, with separate scan enable signals (scan_en0, scan_en1) controlling different segments. This allows independent control of data shifting and launching in different segments, enabling precise detection of slow faults while maintaining implementation flexibility.
Solution Approach 2:
The scan enable signals are dynamically controlled with different timing relationships. By adjusting the relative timing of scan_en0 and scan_en1 transitions, the circuit can adapt to detect various fault conditions (slow-to-rise, slow-to-fall) without requiring fixed rigid control logic.
2Measurement precision
If additional scan flip-flops and control circuits are added to improve fault coverage, then measurement precision improves, but device complexity increases
Solution Approach 1:
The additional scan flip-flops serve multiple functions: they extend the scan chain for broader fault coverage, provide independent control paths for different fault types, and maintain backward compatibility with existing scan testing infrastructure. The control logic universally handles both normal operation and fault detection modes.
Solution Approach 2:
The scan enable control circuit performs preliminary actions by pre-configuring the scan chain state and timing before actual fault detection. The control logic prepares the appropriate scan enable signal transitions in advance, ensuring that the circuit is ready to detect specific fault types without requiring complex real-time decision-making.
3Ease of operation
If scan enable signal transitions slowly to allow easier implementation, then ease of operation improves, but speed of fault detection deteriorates
Solution Approach 1:
The scan enable control is segmented into multiple independent signals (scan_en0, scan_en1) that can transition at different rates and times. This allows the overall system to operate easily with controlled transitions while specific segments can execute faster test operations when needed.
Solution Approach 2:
The scan testing uses periodic clock signals to drive data shifting and launching. By synchronizing multiple scan enable transitions with the periodic clock cycles, the system achieves both ease of control (regular periodic pattern) and high speed (multiple operations per clock cycle through parallel scan chains).
Data Source
AI summary
In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.