Redundancy Circuit Sequence Verification for Memory Programming
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Solution Overview
Problem
Current semiconductor memory devices lack a means to verify if redundancy ROM circuits, programmed using laser cutting, have been programmed in the correct order, leading to potential errors in address replacement, especially with the miniaturization of fuse circuits.
Innovation Solution
A redundancy circuit with a decision circuit that checks the order of redundancy selection signals from multiple redundancy memory circuits, using SR flip-flops and logic circuits to determine if the programming sequence is in the correct ascending order, and outputs a decision signal to detect any sequence reversal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fuse circuits are miniaturized to increase integration density, then device capacity and integration are improved, but programming errors such as erroneous blowing or failure to blow fuses increase
Solution Approach 1:
The patent applies preliminary action by performing a verification test before final product completion. The sequence verification circuit checks the programming order of fuse circuits during a test phase, detecting errors such as erroneous blowing or failure to blow fuses before the product is finalized, thereby preventing defective products from being shipped
Solution Approach 2:
The patent implements feedback through a verification mechanism that monitors the programming process. The sequence verification circuit provides feedback about the programming status of fuse circuits, allowing the system to detect and report programming errors, ensuring that the miniaturized fuse circuits are programmed correctly despite the increased risk from reduced size
2Productivity
If laser cutting is used to program redundancy ROM circuits, then programming speed and automation are improved, but programming errors such as wrong order programming increase
Solution Approach 1:
The patent implements feedback by introducing a sequence verification circuit that monitors the programming process of redundancy ROM circuits. This circuit detects whether fuses are blown in the correct sequence during laser cutting programming, providing feedback that enables detection of programming errors while maintaining the high speed and automation benefits of laser cutting
Solution Approach 2:
The patent replaces manual verification methods with an automated electronic verification system. The sequence verification circuit uses electronic signals and logic circuits to automatically detect programming errors, substituting mechanical or manual checking processes with automated electronic detection, thereby maintaining high productivity while improving reliability
3Adaptability or versatility
If multiple redundancy ROM circuits are provided for multiple address repairs, then repair capability is improved, but verification complexity increases
Solution Approach 1:
The patent applies universality by designing a sequence verification circuit that can handle multiple redundancy ROM circuits through a unified verification mechanism. The verification circuit uses a common counter and comparison logic that works across all redundancy circuits, providing a multi-functional solution that scales with the number of redundancy circuits without proportionally increasing complexity
Solution Approach 2:
The patent applies segmentation by dividing the verification process into modular components: individual fuse blow detection for each redundancy circuit, a central counter mechanism, and a comparison logic unit. This segmented approach allows the verification system to handle multiple redundancy circuits systematically, managing complexity through modular design while maintaining comprehensive verification capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables detection of programming errors in redundancy ROM circuits, ensuring correct address replacement and improving device yield by verifying the programming order of redundancy addresses.
Implementation Method 1
those fuses corresponding to bit positions of address bits of the address information in the redundancy ROM circuit, out of a plural number of fuses corresponding to the number of bits of the address information in the redundancy ROM circuit, are blown by a laser beam
Data Source
AI summary
Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses. In at least one of first to n-th redundancy memory circuits, an address to be substituted by a redundant address is recorded and a redundancy selection signal is output when an access address is coincident with the programmed address. It is presupposed that repair addresses are programmed from the first to the n-th redundancy ROM circuits in an ascending order with regards to address. If it is detected under this condition that a redundancy selection signal has been output from the i+1'st redundancy memory circuit while no redundancy selection signal is being output from the i-th redundancy memory circuit, an SR flip-flop is set and the sequence of the substitution decision outputs is decided to be a reversed sequence.