Redundancy Control Circuit Fuse Inversion for Memory Repair
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Solution Overview
Problem
The reliability of redundancy control circuits in semiconductor memory devices is degraded due to increased residues around the cut area as the number of programmed fuses increases, affecting the integrity of the redundancy control circuit.
Innovation Solution
A redundancy control circuit that selectively performs normal cutting or reverse cutting operations on fuses based on the bit distribution of the repair address, reducing the number of programmed fuses and minimizing residues, by generating a repair address that inverts the defective input address when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of programmed fuses is increased to store repair address information, then the redundancy control circuit can handle more defective memory cells, but the residues around the cut area increase and reliability is degraded
Solution Approach 1:
The patent applies reverse cutting operation where fuses corresponding to bits with majority logic level are NOT cut, while fuses for minority logic level bits are cut. This inverts the conventional approach and reduces the number of cut fuses from potentially 10-20 down to 0-5, minimizing residues and improving reliability while maintaining full adaptability for repair address storage
2Ease of repair
If conventional fuse cutting is performed to store repair address, then the defective memory cells can be replaced, but the residues around the cut area increase when many fuses are programmed
Solution Approach 1:
The patent implements reverse cutting where the majority logic level bits determine which fuses remain intact. This inversion strategy reduces the number of cut fuses and their associated residues, enabling effective repair address storage with minimal harmful residues in the redundancy control circuit
Data Source
AI summary
A redundancy control circuit includes an address fuse circuit and a first circuit. The address fuse circuit includes a plurality of first fuses. Each of the first fuses is configured to be cut based on a result of comparing a number of bits of a defective input address having a first logic level with a number of bits of the defective input address having a second logic level. The address fuse circuit is configured to generate a first address using the first fuses based on a cutting operation that depends on the result of comparing. The first circuit is configured to output either the first address or a second address that is an inverted address of the first address as a repair address, wherein a logic level of each of bits of the repair address is the same as that of the defective input address.


