Redundancy Evaluation Circuit Layout Area Reduction
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Solution Overview
Problem
Conventional redundancy evaluation circuits for semiconductor devices require a large layout area due to the use of multiple multiplexers and transistors, which increases the size of the semiconductor chip and is economically undesirable for defective integrated circuits.
Innovation Solution
A redundancy evaluation circuit design that shares a common stage circuit and precharge transistor among multiple fuse boxes, reducing the number of transistors and multiplexers, and uses a comparator to generate a redundancy enable signal by comparing fuse status and defective element address signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple multiplexers and transistors are used in the redundancy evaluation circuit, then the fuse status evaluation reliability is maintained, but the layout area increases significantly
Solution Approach 1:
The patent merges multiple separate multiplexers into a single shared multiplexer that serves multiple fuse boxes. Instead of having dedicated multiplexers for each fuse box, the invention combines their functions into one unit, reducing the total number of multiplexers from multiple to one, thereby significantly reducing layout area while maintaining evaluation reliability
Solution Approach 2:
The shared multiplexer is designed to perform multiple functions by sequentially serving different fuse boxes. It can multiplex signals from any of the k fuse boxes through control signals, making a single component perform the work of multiple dedicated components, thus reducing overall circuit complexity and layout area
2Area of stationary object
If the number of transistors and multiplexers is reduced to decrease layout area, then the manufacturing cost decreases, but the complexity of circuit design increases
Solution Approach 1:
The patent segments the redundancy evaluation function into modular components: a shared multiplexer unit, a dedicated comparator unit, and multiple fuse box units. This segmentation allows the complex function to be divided into manageable modules with clear interfaces, reducing design complexity despite the reduced component count
Solution Approach 2:
The shared multiplexer acts as an intermediary component that manages signals between the multiple fuse boxes and the comparator. It provides a standardized interface and control mechanism, simplifying the overall design by creating a clear signal flow path rather than requiring complex direct connections between all components
Data Source
AI summary
A redundancy evaluation circuit has (m+1) fuse boxes and a comparator, wherein the m fuse box output a fuse status address signal and the other one fuse box outputs a comparator enable signal. Each fuse box has a common stage circuit and k redundant cells. The k redundant cells shares the precharge transistor and an inverted latch of the common stage circuit, and the fuse in the selected redundant cell affects the output of the corresponding fuse box. The comparator enabled by the comparator enable signal compares the fuse status address signal and a defective element address signal to generate a redundancy enable signal. The redundancy evaluation circuit has a small layout area.