Redundancy Memory Cells for Unrecoverable Wordline Repair
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently repairing fail memory cells, particularly when the number of defective bits exceeds the correction capability of error correction codes, leading to unrecoverable wordlines.
Innovation Solution
A storage device is designed with a redundancy cell array that replaces fail wordlines with redundancy memory cells, utilizing a built-in self-test circuit to identify and repair wordlines with excessive fail bits based on specified criteria, and a repair information memory to manage the mapping of these fail wordlines to redundancy wordlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are used to repair fail memory cells, then data reliability is improved, but the repair capability is insufficient when the number of fail bits exceeds the correction threshold
Solution Approach 1:
The patent performs preliminary detection and identification of fail wordlines during manufacturing or initialization, storing the locations of fail bits in a fail bit map before normal operation begins. This allows the system to proactively prepare repair strategies rather than reacting to errors during data access.
Solution Approach 2:
The patent introduces redundancy wordlines as intermediary structures that mediate between fail wordlines and the main memory array. When a fail wordline is detected, the system uses the redundancy wordline as a substitute pathway, allowing data to be accessed through the redundant structure rather than the defective original line.
2Reliability
If redundancy memory cells are allocated to repair all fail wordlines, then repair coverage is improved, but memory resource utilization deteriorates due to excessive redundancy allocation
Solution Approach 1:
The patent applies repair resources selectively based on the local density and distribution of fail bits. Instead of uniformly allocating redundancy to all wordlines, the system identifies specific fail wordlines that exceed a threshold and targets repair resources only to those locations, making the redundancy allocation non-uniform and adaptive to actual defect patterns.
Solution Approach 2:
The patent changes the parameter of redundancy allocation from a fixed static configuration to a dynamic selective allocation based on fail bit criteria. The system adjusts which wordlines receive redundancy repair by comparing fail bit counts against thresholds, thereby optimizing the balance between repair coverage and resource utilization.
3Device complexity
If conventional error correction codes are used for fail memory cells, then simple error handling is maintained, but unrecoverable wordlines occur when fail bits exceed correction capability
Solution Approach 1:
The patent segments the error handling process into two distinct stages: first, conventional error correction codes handle correctable errors within the main memory array; second, a separate redundancy repair mechanism handles uncorrectable fail wordlines by redirecting access to redundancy structures. This segmentation allows each mechanism to operate within its capability limits without interfering with the other.
Solution Approach 2:
The patent prepares redundancy wordlines in advance as a cushion against potential fail wordlines. By pre-allocating and initializing redundancy structures before failures occur, the system ensures that when uncorrectable errors are detected, the redundancy resources are already ready to assume the workload, preventing data loss without requiring complex real-time reconfiguration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively repairs unrecoverable wordlines by utilizing redundancy resources efficiently, ensuring reliable data storage and retrieval operations even when conventional error correction methods fail.
Implementation Method 1
The magnetization direction of the MTJ may change according to a direction of a current applied to the MTJ
Implementation Method 2
A resistance value of the MTJ may vary according to the magnetization direction of the MTJ
Data Source
AI summary
A storage device includes a main cell array including a plurality of main memory cells connected to a plurality of main wordlines, and a redundancy cell array including a plurality of redundancy memory cells connected to a plurality of redundancy wordlines. The redundancy wordlines are configured to replace a fail wordline including a fail memory cell among the main wordlines. The storage device further includes a repair information memory that stores repair-need-wordline information including matching information for the redundancy wordlines. The matching information is determined by identifying the fail word lines among the main wordlines, and selecting a repair-need-wordline having more fail bits than a specified fail bit criteria. A memory controller performs a read or write operation on a redundancy wordline corresponding to the repair-need-wordline when a request for the main cell array is identified as targeting the repair-need-wordline based on the repair-need-wordline information.