Redundant Bonding-Conductor Structures for 3D Semiconductor Interconnects
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Solution Overview
Problem
Current design and fabrication techniques for three-dimensional semiconductor devices result in relatively lower yields due to unreliable inter-chip connections, which hinders the exploitation of performance gains offered by the 3D configuration.
Innovation Solution
The implementation of redundant bonding-conductor structures, including conductor-filled vias and pad structures, to establish reliable connections between chips in a stacked IC configuration, allowing for face-up or face-down orientations and enhancing connection reliability through redundant conductive-bonding features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inter-chip connection techniques are used in three-dimensional semiconductor devices, then device integration is achieved, but connection reliability is poor resulting in lower yields
Solution Approach 1:
The patent implements redundant bonding-conductor structures including multiple via structures and pad structures that provide backup connection paths. If primary connection paths fail, the redundant structures ensure continued functionality, thereby improving connection reliability and manufacturing yield in three-dimensional semiconductor devices
2Productivity
If more components are added to increase device functionality, then device performance improves, but horizontal area occupied increases
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional stacked configuration by forming multiple semiconductor structures at different vertical levels. Components are arranged in stacked layers connected by vertical bonding-conductor structures, enabling increased device functionality without proportionally increasing horizontal footprint
Data Source
AI summary
A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.