Redundant ECC Bit Storage With Majority Voting in Memory Cells

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Solution Overview

Problem

Conventional semiconductor memory systems with error correction coding (ECC) face reliability issues when ECC bits are damaged, as they can render error correction operations invalid.

Innovation Solution

The implementation of a semiconductor device with multiple memory cells and ECC cells, where ECC bits are redundantly stored in pairs or groups, allowing for simultaneous reading and writing of complementary bits, and utilizing a determination logic circuit for majority voting to generate ECC outputs, enhancing ECC bit reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If ECC bits are stored in memory cells together with data bits, then data storage is simplified, but reliability decreases when ECC bits are damaged

Engineering Contradiction:

Improvedata storage simplicityVSAvoidECC bit reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The memory device is segmented into separate data storage cells and ECC storage cells. The ECC bits are stored in dedicated ECC cells that are spatially separated from the data cells, allowing independent protection and recovery of ECC bits without affecting data storage operations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple copies of ECC bits are stored in redundant ECC cells. When an ECC bit is damaged or lost, the system can retrieve the correct value from the redundant copies, ensuring continuous operation without data loss.

Inventive Principle:

Principle #26Copying

2Reliability

If redundant ECC bit storage is implemented, then reliability increases, but device complexity increases

Engineering Contradiction:

ImproveECC bit reliabilityVSAvoidmemory structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The read and write operations for redundant ECC bits are merged into unified circuit paths. The same bit lines and word lines are used for both reading from and writing to ECC cells, reducing the number of separate circuit components needed.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Instead of storing every possible bit state, the system uses a limited set of redundant ECC cells that provide sufficient protection for the required reliability level. The redundancy ratio is optimized to provide adequate error correction without excessive storage overhead.

Inventive Principle:

Principle #16Partial or excessive action

3Speed

If simultaneous reading of complementary bits is enabled, then read speed increases, but write operation complexity increases

Engineering Contradiction:

Improveread speedVSAvoidwrite circuit complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Complementary ECC bits are pre-stored in paired ECC cells during the write operation. This preliminary preparation allows the read circuit to simultaneously access both bits without requiring complex synchronization or sequential reading operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A control circuit acts as an intermediary to manage the write operations to paired ECC cells. The control circuit coordinates the writing of complementary bits to ensure proper timing and data integrity, simplifying the overall write process despite the simultaneous read capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20100223532A1Systems, devices and methods using redundant error correction code bit storage

Publication Date: 2010.09.02 SAMSUNG ELECTRONICS CO LTD

AI summary

A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.