Redundant Micro-Loop Via Structure for IC Yield
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Solution Overview
Problem
The manufacturing of very large scale integrated circuits (VLSI) is challenged by the sensitivity of small feature widths and spacing, leading to increased risk of chip failure due to single vias, which are difficult to manufacture and prone to defects, necessitating improved redundant via structures to enhance yield and reduce manufacturing complexity.
Innovation Solution
The implementation of a redundant micro-loop structure in integrated circuit design, which includes additional vias and wires forming alternative electrical paths to ensure connectivity even if a primary via is defective, without using wrong-way wiring, thus maintaining high wiring density and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single vias are used to connect wiring levels, then wiring density is maintained, but manufacturing reliability deteriorates due to high sensitivity to defects and open circuits
Solution Approach 1:
The patent divides the single via connection into multiple separate vias distributed along the wiring path. Instead of relying on one critical via, the connection is segmented into several redundant vias, so that if one via fails, other segments maintain connectivity. This segmentation transforms the single-point-failure structure into a distributed-reliability structure.
Solution Approach 2:
The patent preemptively adds redundant vias alongside the primary via connection before manufacturing defects can occur. These redundant paths serve as pre-prepared backup connections that cushion against potential via failures, ensuring that even if the primary via opens or becomes high-resistance, the circuit remains functional.
2Reliability
If redundant via structures are implemented, then manufacturing yield improves, but wiring density decreases due to additional structure space requirements
Solution Approach 1:
The patent implements partial redundancy by adding vias only at critical connection points where via failures would cause circuit failure, rather than providing complete redundancy throughout all wiring paths. This selective approach achieves sufficient yield improvement while minimizing the area overhead associated with redundant structures.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking vias at the same lateral position across multiple wiring levels, creating three-dimensional via structures. This allows redundant connection paths to be formed in the vertical dimension rather than consuming additional lateral wiring space, thereby maintaining wiring density while providing redundancy.
3Productivity
If feature widths and spacing are reduced to increase integration density, then circuit functionality improves, but sensitivity to random defects increases
Solution Approach 1:
The patent applies different design qualities to different regions of the circuit. In areas with reduced feature widths and spacing where integration density is maximized, the patent locally enhances reliability by adding redundant vias at critical connection points. This localized quality enhancement addresses the increased defect sensitivity in high-density regions without reducing integration density elsewhere.
Data Source
AI summary
An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.