Reference Voltage Buffering With Two-Phase Offset Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing reference voltages in analog-to-digital and digital-to-analog converters suffer from offset and noise errors, which affect the accuracy and linearity of signal conversion processes.
Innovation Solution
A circuit and method involving an amplifier, two buffers, and a capacitor operate in two phases to sample and correct for intrinsic offset and mismatch errors by forming closed loops that exclude or include the capacitor, using switches to manage the loop configurations and store offset voltage on the capacitor for subtraction during the second phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference voltage is used in ADCs and DACs, then the conversion process can be performed, but offset and noise errors reduce the accuracy and linearity
Solution Approach 1:
The circuit performs preliminary offset sampling during a first phase before the actual conversion operation. The capacitor stores the offset voltage sampled from the reference voltage, which is then subtracted during the second phase to correct the reference voltage, thereby eliminating offset errors before they affect conversion accuracy
Solution Approach 2:
The circuit implements a feedback mechanism where the offset voltage is sampled from the reference voltage output and fed back through the capacitor to be subtracted from subsequent reference voltage outputs. This closed-loop feedback continuously corrects the reference voltage to maintain high conversion accuracy
2Object-affected harmful factors
If buffering strategies are employed to protect reference voltage integrity, then noise is reduced, but circuit complexity increases
Solution Approach 1:
The buffering function is segmented into two distinct phases: a first phase for offset sampling and calibration, and a second phase for actual reference voltage output. This segmentation allows the circuit to perform noise reduction and offset correction separately, reducing the need for continuous complex buffering mechanisms
Solution Approach 2:
The circuit uses periodic switching between two operational phases - a calibration phase where the capacitor samples offset voltage, and an output phase where the corrected reference voltage is provided. This periodic action allows noise reduction through controlled buffering only when necessary, simplifying the overall circuit design
3Manufacturing precision
If the reference voltage is stabilized to reduce offset errors, then conversion linearity improves, but bandwidth is reduced
Solution Approach 1:
The offset correction is performed as a preliminary action before the main conversion operation. By sampling and storing the offset voltage on the capacitor during the first phase, the circuit establishes the correction value in advance, allowing high-linearity output during the second phase without requiring continuous stabilization that would limit bandwidth
Solution Approach 2:
The circuit dynamically switches between two operational modes using switches that connect or disconnect the capacitor in different phases. During the calibration phase, the capacitor is connected to sample offset; during the output phase, it is connected to provide correction. This dynamic operation allows the circuit to achieve high linearity when needed while maintaining high bandwidth through rapid phase switching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable, low-offset reference voltage with high bandwidth and reduced errors, suitable for driving capacitive loads, thereby enhancing the accuracy and efficiency of converters like SAR-ADCs.
Implementation Method 1
sampling a voltage difference between an output of the second buffer and the reference voltage node across the capacitor
Data Source
AI summary
In accordance with an embodiment, a circuit includes an amplifier comprising a first input coupled to a reference voltage node, a first buffer having an input coupled to an output of the amplifier, a second buffer having an input coupled to the output of the amplifier, and a capacitor. A method of operating the circuit includes during a first phase of operation: forming a first closed loop including the amplifier and the first buffer and excluding the capacitor and the second buffer, and sampling a voltage difference between an output of the second buffer and the reference voltage node across the capacitor; and during a second phase of operation, forming a second closed loop including the amplifier, the first buffer, and the capacitor with the sampled voltage difference stored thereon, and excluding the second buffer.