Reference Clock Duty Cycle Correction for Fine Delay Detection
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Solution Overview
Problem
Conventional duty cycle correction circuits face challenges in accurately detecting duty cycles due to mismatched delays in buffers, leading to increased hardware costs as resolution and clock signal period increase, especially in high-speed data transmission systems.
Innovation Solution
A duty cycle correction circuit comprising a first duty cycle detecting circuit, a reference clock generating circuit, a second duty cycle detecting circuit, and adjusting circuits that use reference clock signals to achieve finer resolution and reduce hardware costs by minimizing time differences between clock signals, thereby improving duty cycle adjustment precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional TDC with multiple buffers is used to adjust duty cycle, then the duty cycle can be adjusted, but mismatch in delay amount between buffers occurs making accurate duty cycle detection difficult
Solution Approach 1:
A reference clock signal is introduced as an intermediary to synchronize the operation of delay lines and buffers. The reference clock provides a common timing基准 that ensures consistent delay measurement across different buffer stages, eliminating the mismatch problem caused by independent buffer operations.
Solution Approach 2:
The patent applies equipotentiality by ensuring all delay measurement operations occur under identical timing conditions using the reference clock. This creates an equipotential timing environment where all buffers operate from the same clock edge, ensuring consistent delay amounts across the system.
2Measurement precision
If the resolution of the TDC is enhanced to improve duty cycle detection precision, then the measurement precision improves, but the hardware cost increases
Solution Approach 1:
The duty cycle detection is divided into two segments: a first duty cycle detecting circuit for coarse detection and a second duty cycle detecting circuit for fine detection. This segmentation allows the system to achieve high resolution without requiring a single complex high-resolution TDC, thereby reducing overall hardware cost.
Solution Approach 2:
The patent uses partial action by implementing two levels of detection precision rather than one extremely high-resolution system. The first detecting circuit handles the majority of the detection range, while the second circuit provides fine-tuning, avoiding the need for excessive hardware resources to achieve full precision across the entire range.
3Adaptability or versatility
If the period of the clock signal is increased to widen the duty cycle adjustment range, then the adaptability improves, but the hardware cost increases due to larger delay requirements
Solution Approach 1:
The patent implements dynamic scaling of the reference clock frequency based on the input clock signal characteristics. When the input clock period is large, the reference clock is scaled down proportionally, maintaining consistent delay line requirements regardless of the absolute clock period, thus achieving wide adaptability without increasing hardware cost.
Solution Approach 2:
The system dynamically changes the reference clock frequency parameter to match the input clock signal characteristics. This parameter adaptation allows the fixed hardware delay lines to effectively handle a wide range of clock periods by adjusting the timing reference rather than requiring hardware scaling.
4Measurement precision
If a separate synchronous delay line is added to compensate for buffer delay, then the delay accuracy improves, but the device complexity increases
Solution Approach 1:
The patent merges the delay compensation function into the existing delay line structure by using the same delay lines for both the input clock and reference clock with coordinated control. This eliminates the need for separate synchronous delay lines, as the compensation is achieved through the integrated delay structure and reference clock synchronization.
Data Source
AI summary
A duty cycle correction circuit includes a first duty cycle detecting circuit configured to detect a duty cycle of a clock signal with a first resolution; a reference clock generating circuit configured to generate a reference clock signal by adjusting a phase of the clock signal; a second duty cycle detecting circuit configured to detect a duty cycle of the clock signal with a second resolution according to the reference clock signal and the clock signal, the second resolution being finer than the first resolution; a first duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more first control signals output from the first duty cycle detecting circuit; and a second duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more second control signals output from the second duty cycle detecting circuit.