Frequency-Divided Reference Clock Synchronization for PLL Phase Noise
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Solution Overview
Problem
Phased array antennas face challenges in Local Oscillator (LO) frequency planning due to interference between Phase Locked Loops (PLLs) operating at similar frequencies, which degrades noise performance and throughput in wireless communication systems.
Innovation Solution
A system for synchronizing digital reference signals for Digital-to-Analog Converter (DAC) serializers and Analog-to-Digital Converter (ADC) deserializers, using a Phase Locked Loop (PLL) to generate an ADC/DAC reference signal, and aligning a SET signal with the phase of this reference signal to synchronize digital reference clocks for serializers and deserializers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLLs are enabled simultaneously to support carrier aggregation frequency band combinations, then the system can operate over different frequency bands, but the controlled oscillators in the PLLs interfere with each other when running at the same or similar frequencies, degrading noise performance
Solution Approach 1:
The patent applies preliminary action by generating and distributing the reference clock signal to all PLLs before they are enabled to operate. This ensures that each PLL receives a synchronized reference signal with known phase relationship, allowing them to be enabled simultaneously without mutual interference. The reference clock is prepared in advance and distributed through a common clock distribution network, establishing a predetermined phase relationship before the PLLs begin frequency multiplication.
2Speed
If PLLs run at frequencies with harmonic relations, then the system can achieve frequency multiplication for different LO frequencies, but harmonic interference occurs when a harmonic of one PLL frequency equals another PLL frequency, degrading throughput
Solution Approach 1:
The patent uses a common reference clock signal as an intermediary that mediates the frequency relationships between multiple PLLs. By deriving all PLL output frequencies from a single reference clock through frequency multiplication, the system establishes a hierarchical frequency structure where harmonics are predictable and controllable. The reference clock acts as a master synchronizer that prevents uncontrolled harmonic interference by ensuring all PLLs are phase-coherent with respect to a common timing source.
3Device complexity
If frequency division is used to generate serializer and deserializer reference clocks from the ADC/DAC reference signal, then the clocks can be derived from a single source, but phase ambiguity and delay uncertainty arise without synchronization
Solution Approach 1:
The patent implements feedback by using the same frequency-divided reference clock signal that clocks the frequency dividers themselves. This creates a closed-loop synchronization system where the reference clocks for serializers and deserializers are derived from and feedback to the same source, ensuring automatic phase alignment. The feedback mechanism ensures that any phase shifts or delays are consistent across all divided clock paths, eliminating phase ambiguity without requiring additional synchronization circuitry.
Data Source
AI summary
Systems and techniques for synchronizing serializer and deserializer digital reference clocks are described. An example method includes activating a phase locked loop (PLL) to generate an ADC/DAC reference signal, obtaining a DAC Enable (DAC_EN) signal, generating, based on the DAC_EN signal, a SET signal aligned with a phase of the ADC/DAC reference signal, generating, based on the ADC/DAC reference signal, a serializer digital reference clock for a serializer coupled to the DAC, and generating, based on the ADC/DAC reference signal and the SET signal, a deserializer digital reference clock for a deserializer coupled to the ADC. The serializer digital reference clock and the deserializer digital reference clock are each respectively generated by frequency division of the ADC/DAC reference signal. The serializer digital reference clock and the deserializer digital reference clock are synchronized to a known phase based on the SET signal.