Reference Dice Selection for Semiconductor Test Optimization
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Solution Overview
Problem
The exponential growth in transistor density in semiconductor products due to advances in semiconductor process technology strains test systems, leading to increased complexities, costs, and challenges in ensuring quality and reliability, as traditional testing methods become inadequate for high-volume production of complex integrated circuits.
Innovation Solution
A system and method for semiconductor testing that identifies and selects reference dice within a wafer to represent a group of dice assumed to respond similarly to testing, allowing for differentiated test flows between reference and non-reference dice, optimizing test efficiency and reducing costs by tailoring test protocols based on the characteristics of these selected dice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional testing methods are used for high-volume production of complex integrated circuits, then quality and reliability can be maintained, but test time and cost increase significantly
Solution Approach 1:
The wafer is divided into groups of dice, with selected reference dice representing each group. This segmentation allows different testing approaches for reference versus non-reference dice, enabling reduced test time for non-reference dice while maintaining quality through reference-based validation
Solution Approach 2:
Reference dice serve as representative copies of their respective groups. By testing reference dice thoroughly and using their results to inform testing of non-reference dice, the system reduces overall test time while maintaining reliability through the representative sampling approach
2Reliability
If comprehensive testing is performed on all dice, then quality assurance is maintained, but manufacturing cost increases
Solution Approach 1:
Different testing protocols are applied to different types of dice within the same wafer. Reference dice receive comprehensive testing, while non-reference dice receive reduced testing based on reference die results. This local differentiation maintains quality assurance where needed while reducing overall manufacturing cost
Solution Approach 2:
Instead of applying the same comprehensive testing to all dice (excessive action), the system applies comprehensive testing only to reference dice (partial action) and uses their results to determine appropriate testing for non-reference dice, thereby reducing manufacturing cost while maintaining adequate quality assurance
3Reliability
If more transistors and structures are tested due to increased density, then product reliability improves, but test system complexity increases
Solution Approach 1:
The testing system segments dice into groups with representative reference dice. This segmentation simplifies test system operation by providing clear criteria for selecting and testing reference dice versus non-reference dice, reducing the complexity burden that would otherwise result from testing every individual transistor and structure
Data Source
AI summary
Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.