Reference Read Timing for Threshold Selector Memory Drift

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Solution Overview

Problem

Threshold selector devices in memory systems experience threshold voltage drift over time, limiting the memory read window and making highly reliable and low latency operations challenging.

Innovation Solution

Implementing a reference memory cell to track and mitigate threshold voltage drift in data memory cells by writing a predetermined value to the reference cell each time data is written, using its drifted threshold voltage to adjust for drift in corresponding data cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If threshold selector devices are used in memory systems, then memory storage capability is achieved, but threshold voltage drift occurs over time limiting read reliability

Engineering Contradiction:
Improveread reliabilityVSAvoidthreshold voltage stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by writing a predetermined reference value to the reference memory cell before reading data. This reference cell is updated in advance with a known value, allowing the read operation to compare against a stable baseline that compensates for threshold voltage drift that has already occurred during the write phase. This preliminary reference establishment enables accurate reading even though drift has happened.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the reference memory cell to provide a baseline that reflects the current threshold voltage state after drift. The read operation uses this feedback information from the reference cell to compensate for the drift in data memory cells, effectively correcting the threshold voltage shift and maintaining read reliability.

Inventive Principle:
Principle #23Feedback

2Stability of the object's composition

If threshold voltage drift is not compensated, then device complexity remains low, but read window stabilizes poorly over time

Engineering Contradiction:
Improveread window stabilityVSAvoidmemory cell structure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent uses copying by creating a reference memory cell that replicates the structure and drift characteristics of the data memory cells. This copy experiences the same threshold voltage drift, allowing it to serve as an accurate baseline for compensation. The reference cell is a structural copy that mirrors the behavior of data cells without requiring complex active compensation circuitry.

Inventive Principle:
Principle #26Copying

3Measurement precision

If reference memory cell is written every time data is written, then drift tracking accuracy improves, but write operation time increases

Engineering Contradiction:
Improvedrift tracking precisionVSAvoidwrite operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges the reference value writing operation with the data write operation by performing both writes during the same write cycle. The reference memory cell and data memory cells are written simultaneously or in close succession, combining two write operations into one coordinated action. This reduces the total time compared to writing the reference cell separately before and after data writes.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20260004846A1Apparatus and methods for reference read techniques for threshold selector device memory
Publication Date: 2026.01.01 SANDISK TECHNOLOGIES LLC
  • US20260004846A1 patent drawing
  • US20260004846A1 patent drawing
  • US20260004846A1 patent drawing

AI summary

An apparatus includes memory array having a first memory cell including a first two-terminal element having first and second threshold voltages, a second memory cell including a second two-terminal element having third and fourth threshold voltages, and a control circuit coupled to the memory array. The control circuit is configured to cause the first two-terminal element to have the first threshold voltage, and cause the second two-terminal element to have either the third threshold voltage or the fourth threshold voltage, apply a third voltage signal that increases at a first ramp rate to the first memory cell and the second memory cell, determine that the first memory cell switches from a non-conducting state to a conducting state, and read the second memory cell using the third voltage signal a first predetermined delay time after the first memory cell switches from the non-conducting state to the conducting state.