Referenceless Clock Recovery Using Counter-Based Error Detection
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Solution Overview
Problem
Current clock and data recovery circuits for high-speed serial communication systems face challenges in achieving low bit error rates and efficient power usage due to the need for reference oscillators, which increase semiconductor die area and power consumption, and are limited by the complexity of evolving serial data protocols.
Innovation Solution
The implementation of 'referenceless' clock and data recovery circuits that use counter-based frequency and phase error detectors to generate recovered clock signals without a reference oscillator, eliminating the need for separate loop filters and reducing power consumption by dynamically controlling the voltage-controlled oscillator based on edge count differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a reference oscillator is used in clock and data recovery circuits, then frequency stability is improved, but semiconductor die area and power consumption increase
Solution Approach 1:
The patent removes the reference oscillator from the clock and data recovery circuit, extracting the frequency stability function to be achieved through alternative means (phase detectors and VCO without external reference), thereby reducing die area while maintaining operational stability
Solution Approach 2:
The voltage-controlled oscillator serves multiple functions: generating the recovered clock signal and providing frequency stability through feedback control without requiring a separate reference oscillator, thus reducing overall circuit complexity and die area
2Stability of the object's composition
If a reference oscillator is used in clock and data recovery circuits, then frequency stability is improved, but power consumption increases
Solution Approach 1:
The reference oscillator is extracted from the circuit architecture, eliminating its power consumption while achieving frequency stability through the phase detector and VCO feedback mechanism alone
Solution Approach 2:
The circuit achieves frequency stability through self-service feedback control where the phase detectors monitor and adjust the VCO output frequency based on phase error detection, eliminating the need for external power-hungry reference oscillators
3Area of stationary object
If counter-based frequency and phase error detectors are used to eliminate reference oscillators, then die area and power consumption are reduced, but measurement precision of frequency and phase errors may worsen
Solution Approach 1:
The error detection function is segmented into separate frequency error detectors and phase error detectors, each using counter-based mechanisms to independently measure and control frequency and phase deviations, maintaining precision through dedicated measurement circuits
Solution Approach 2:
The counter-based detectors implement feedback control where measured frequency and phase errors are continuously fed back to adjust the VCO, improving measurement precision through iterative correction and averaging effects
4Device complexity
If separate loop filters are eliminated, then device complexity is reduced, but control precision of the voltage-controlled oscillator may worsen
Solution Approach 1:
The frequency control and phase control functions are merged into a unified feedback mechanism where the same VCO is controlled by combined frequency error and phase error signals, eliminating separate loop filters while maintaining control precision through integrated error correction
Solution Approach 2:
The voltage-controlled oscillator serves as a universal control point that responds to both frequency and phase error corrections through a unified feedback path, replacing multiple specialized filters with a single multi-functional control mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances stability and reduces semiconductor die area and power consumption, enabling efficient high-speed data recovery with lower bit error rates and adaptability to evolving serial standards, particularly in constrained spaces like mobile devices.
Implementation Method 1
first circuitry including a voltage-controlled oscillator, the first circuitry configured to generate a recovered clock signal
Data Source
AI summary
Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.