Reforming Resistive Memory Cells via High-Voltage Pulses
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Solution Overview
Problem
Resistive memory cells in nonvolatile memory devices experience a decrease in the difference between their HIGH and LOW resistive states over time and with cyclic use, leading to read and write inaccuracies and errors, as the sense amplifier may not be able to distinguish between the states when the difference is less than a predetermined threshold, resulting in failed memory cells.
Innovation Solution
A method and system for reforming memory cells by applying higher voltages or currents than those used in read and write cycles to reset the resistive states, increasing the difference between HIGH and LOW resistive states to levels distinguishable by detection circuits, thereby extending the endurance and useful life of the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If higher voltages or currents are applied to reform memory cells, then the difference between HIGH and LOW resistive states is increased, but the risk of damaging the memory cell increases
Solution Approach 1:
The patent applies parameter changes by systematically varying voltage and current parameters during the reform process. Different voltage levels, pulse durations, and current magnitudes are used to achieve the desired resistive state differentiation while staying within safe operational limits. This involves adjusting parameters such as applying voltages between 2-5V for reform compared to lower read voltages, and controlling pulse widths to optimize the reform effect without causing damage.
Solution Approach 2:
The reform process utilizes periodic action through pulsed voltage and current application. Instead of continuous high-voltage application, the system applies periodic pulses with specific duty cycles and frequencies. This allows the memory cell material to respond to the electric fields in a controlled manner, achieving reform through cumulative effect of multiple pulses while providing intervals for thermal and electrical relaxation, thereby preventing damage.
2Productivity
If the memory cell is used for multiple read and write cycles, then the memory cell experiences wear, but the difference between resistive states decreases leading to read errors
Solution Approach 1:
The patent implements preliminary action by performing reform operations proactively before the memory cell's resistive states deteriorate to unusable levels. The system monitors write cycle counts and resistive state differences, triggering reform operations at predetermined intervals or when thresholds are approached. This preventive reform restores the resistive state differentiation before it degrades to cause read errors, extending the effective endurance of the memory cell.
Solution Approach 2:
The system employs feedback mechanisms to monitor the health and performance of memory cells during operation. By continuously or periodically measuring the difference between HIGH and LOW resistive states, the system can detect degradation trends and trigger reform operations when needed. This feedback-driven approach optimizes the balance between productivity and measurement precision by applying reform only when necessary to maintain state distinction accuracy.
3Reliability
If reform operations are performed frequently, then the resistive states are maintained, but the overall memory cell lifespan is reduced
Solution Approach 1:
The patent applies partial action by performing reform operations selectively rather than continuously. The system determines when reform is needed based on monitored parameters such as write cycle counts, detected read errors, or measured resistive state differences. Reform is applied partially - only to memory cells that show signs of degradation - rather than to all cells uniformly. This selective approach maintains state distinction reliability while minimizing the total number of reform operations to preserve memory cell lifespan.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reforming process effectively resets the resistive states of memory cells to levels that are distinguishable by detection circuits, ensuring accurate read and write operations and extending the lifespan of the memory cells by maintaining a significant difference between their states.
Implementation Method 1
Each of the memory cells includes a resistance, which indicates a state of the corresponding memory cell. The resistance may be in a HIGH resistive state indicating that the memory cell is storing a '1' or may be in a LOW resistive state indicating that the memory cell is storing a '0'.
Implementation Method 2
As a first example, in order to determine a resistive state of a memory cell, a voltage can be applied across the resistance of the memory cell. A current through the resistance can then be detected and is indicative of the resistive state. As another example, a current can be supplied to the resistance of the memory cell. A voltage across the resistance can then be detected and is indicative of the resistive state.
Data Source
AI summary
A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle.