Refresh Control Circuit for Dynamic Memory Bank Addressing
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Solution Overview
Problem
Conventional semiconductor memory devices experience inefficiencies in power consumption due to wasteful refresh operations, as they refresh all memory banks regardless of data presence, leading to increased power usage and reduced efficiency.
Innovation Solution
A refresh control circuit and method that generates bank address signals to selectively identify and refresh memory banks with the longest refresh cycles, optimizing the refreshing operation to reduce power consumption by performing refreshes at the shortest refresh cycles of selected banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory banks are refreshed regardless of data presence, then data reliability is maintained, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating the refresh treatment of different memory banks based on their actual data storage status. Instead of uniform refresh across all banks, the system identifies and refreshes only those memory banks that actually contain data, thereby reducing unnecessary power consumption while maintaining data reliability where needed.
Solution Approach 2:
The patent extracts the unnecessary refresh operations from the overall refresh process. By detecting which memory banks contain actual data and excluding those without data from the refresh cycle, the system removes wasteful power consumption while preserving the essential refresh function for banks that do contain data.
2Use of energy by moving object
If Partial Array Self Refresh is implemented to refresh only memory banks with data, then power consumption is reduced, but the complexity of determining which banks need refreshing increases
Solution Approach 1:
The patent implements self-service by enabling memory banks to self-indicate their data storage status through dedicated signal lines. Each memory bank automatically provides information about its own state, allowing the control circuit to make intelligent refresh decisions without complex external monitoring systems, thus reducing overall system complexity while achieving power savings.
Solution Approach 2:
The patent employs feedback mechanisms where memory banks provide status information about their data presence to the control circuit. This feedback loop enables the control circuit to adjust refresh operations based on actual conditions, reducing power consumption while maintaining manageable complexity through systematic information gathering and response.
Data Source
AI summary
A refresh control circuit and method thereof and a bank address signal change circuit and methods thereof. The bank address signal change circuit may receive bank address signals from a bank address signal generation circuit. The received bank address signals may designate a first at least one of a plurality of memory banks. The bank address signal change circuit may determine whether the first at least one designated memory bank is associated with the longest refresh cycles from among the plurality of memory banks. Based on the determination, the bank address signal change circuit may generate a plurality of bank address signal change signals designating a second at least one of the plurality of memory banks. A refresh operation circuit may perform a refreshing operation on the second at least one memory banks in accordance with the bank address signal change signals. The bank address signal generation circuit, bank address signal change circuit and refresh operation circuit may each be included in a refresh control circuit.