Register Allocation Using Temporary Registers for JIT Loop Conflicts
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Solution Overview
Problem
Just-in-time compilation (JIT) compilers face conflicts during register allocation in execution loops, leading to inefficient native code execution due to time-consuming memory operations required to resolve conflicts, which hampers the performance of Java programs.
Innovation Solution
The implementation of temporary registers to resolve conflicts in register allocation by selecting physical registers based on original and target allocations, allowing for efficient data movement and allocation changes using processor-executed instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a linear scan algorithm is used for register allocation, then register allocation can be performed efficiently in a single linear scan, but conflicts in execution loops require time-consuming memory operations to resolve
Solution Approach 1:
The patent segments the register allocation process into two distinct phases: a fast linear scan phase that performs initial register allocation, and a conflict resolution phase that handles only the specific loop-related conflicts. This segmentation allows the majority of register allocation to proceed efficiently while isolating the time-consuming conflict resolution to a targeted subset of cases.
Solution Approach 2:
The patent introduces an intermediary data structure (loop interference graph) that captures loop-specific register conflicts separately from the general register allocation process. This intermediary representation enables efficient identification and resolution of conflicts without requiring complete re-analysis of all register allocations, thus reducing time consumption.
2Adaptability or versatility
If local variables are loaded from memory during native code execution, then all variables can be accessed, but execution becomes time-consuming
Solution Approach 1:
The patent performs preliminary identification of loop-carried dependencies and register conflicts before generating the final native code. By pre-analyzing which variables require memory loading versus register access during loop execution, the system optimizes the placement of variables in registers versus memory, ensuring that frequently accessed loop variables remain in registers for faster access.
Solution Approach 2:
The patent applies different storage strategies to different variables based on their specific usage patterns within loops. Variables that are frequently accessed and defined within loop bodies are allocated to registers, while variables accessed less frequently or only in specific contexts are allowed to be loaded from memory. This localized optimization improves overall execution speed without compromising variable accessibility.
Data Source
AI summary
System and methods are provided for register allocation. An original code block and a target code block associated with a branch of an execution loop are determined. An original allocation of a plurality of physical registers to one or more original variables associated with the original code block is detected. A target allocation of the plurality of physical registers to one or more target variables associated with the target code block is determined. One or more temporary registers are selected from the plurality of physical registers based at least in part on the original allocation and the target allocation. The original allocation is changed to the target allocation using the selected temporary registers. Specifically, one or more instructions are generated to change the original allocation to the target allocation using the selected temporary registers. The instructions are executed using one or more processors.