Register Bank Segmentation for Dedicated Processor Throughput

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Solution Overview

Problem

Processing systems face inefficiencies when executing operations of a particular type, as they often rely on general-purpose processors, which are not optimized for specific tasks, leading to suboptimal performance in terms of speed, power usage, and resource allocation.

Innovation Solution

A processing system comprising a dedicated processor adapted for specific operations, a program processor, and an interfacing module that utilizes multiple register banks to control data flow, allowing concurrent execution of operations by providing access to one register bank for execution while loading data into another, thereby maximizing the dedicated processor's execution time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single register bank is used for data storage and execution, then the system structure is simple, but the dedicated processor cannot execute operations continuously, reducing productivity

Engineering Contradiction:
Improveexecution continuityVSAvoidregister bank structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The register bank is divided into multiple segments (first register bank and second register bank), allowing the dedicated processor to access one segment while the CPU accesses another segment simultaneously. This segmentation enables continuous operation by eliminating waiting time for data loading.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The CPU loads data into the second register bank in advance while the dedicated processor is executing operations using the first register bank. This preliminary action ensures that data is ready before the dedicated processor needs it, enabling seamless transition between operations without idle time.

Inventive Principle:
Principle #10Preliminary action

2Speed

If the dedicated processor waits for data loading between operations, then data accuracy is maintained, but processing time increases, reducing speed

Engineering Contradiction:
Improveprocessing speedVSAvoidwaiting time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The system maintains continuous useful action by overlapping the data loading phase (CPU writing to second register bank) with the execution phase (dedicated processor reading from first register bank). This eliminates idle waiting time and ensures the dedicated processor is always engaged in productive work.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

Data is prepared in advance in the second register bank before the dedicated processor completes its current operation. This preliminary preparation eliminates the need for waiting, as the data is already loaded and ready for immediate use when the current operation finishes.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If sequential execution is used (complete one operation before starting the next), then resource allocation is simple, but overall processing time increases, reducing productivity

Engineering Contradiction:
ImprovethroughputVSAvoiddata flow control
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The data flow is segmented into two independent paths: one path for the dedicated processor reading from the first register bank, and another path for the CPU writing to the second register bank. This segmentation allows parallel operations without complex coordination, as each path operates independently with its own register bank.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The two register banks act as intermediaries that decouple the CPU and dedicated processor, allowing them to operate independently without direct coordination. The interface module simply manages which register bank is active for the dedicated processor, simplifying the control logic while enabling parallel operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10387155B2Controlling register bank access between program and dedicated processors in a processing system
Publication Date: 2019.08.20 NORDIC SEMICONDUCTOR
  • US10387155B2 patent drawing
  • US10387155B2 patent drawing
  • US10387155B2 patent drawing

AI summary

A processing system includes a program processor for executing a program, and a dedicated processor for executing operations of a particular type (e.g. vector processing operations). The program processor uses an interfacing module and a group of two or more register banks to offload operations of the particular type to the dedicated processor for execution thereon. While the dedicated processor is accessing one register bank for executing a current operation, the interfacing module can concurrently load data for a subsequent operation into a different one of the register banks. The use of multiple register banks allows the dedicated processor to spend a greater proportion of its time executing operations.