Register Clock Driver with Delayed Sink Clock for Timing Margin
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Solution Overview
Problem
Semiconductor memory devices face timing violations due to insufficient propagation delay margins in high-speed and low-speed frequency ranges, necessitating a register clock driver with a constant propagation delay margin independent of operating frequency.
Innovation Solution
A register clock driver with a source circuit and sink circuit, utilizing different clock signals and a clock delay mechanism to maintain a consistent propagation delay margin across varying frequencies, incorporating a phased locked loop to generate delayed clock signals for synchronized operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a register clock driver operates in high-speed frequency range, then productivity is improved, but timing violation occurs due to insufficient propagation delay margin
Solution Approach 1:
The patent applies dynamics by making the clock signal phase adjustable based on operating conditions. The register clock driver dynamically changes the clock phase shift amount according to the operating frequency range to maintain constant propagation delay margin. This is achieved through control logic that detects the operating frequency and adjusts the clock phase accordingly, allowing the system to adapt its timing characteristics to different speed requirements while maintaining reliability.
2Reliability
If a register clock driver operates in low-speed frequency range, then reliability is improved with sufficient propagation delay margin, but productivity decreases
Solution Approach 1:
The system dynamically adjusts the clock phase shift amount based on the detected operating frequency range. When operating in low-speed range, the control logic reduces the clock phase shift to maximize productivity while maintaining the minimum required propagation delay margin. This dynamic adjustment allows the register clock driver to optimize for speed when conditions permit, rather than being constrained by conservative timing margins designed for high-speed operation.
3Reliability
If different clock phases are applied to source and sink circuits, then propagation delay margin becomes constant across frequencies, but device complexity increases
Solution Approach 1:
The patent implements a universal clock distribution mechanism where a single clock signal is distributed to both source and sink circuits, but with adjustable phase shifting capability. The clock distribution network is designed to provide the same clock signal to multiple circuits while allowing dynamic phase adjustment. This multi-functional approach allows the system to maintain constant propagation delay margin across different operating conditions without requiring entirely separate clock networks for different frequency ranges, thereby reducing overall complexity.
Solution Approach 2:
The patent introduces a clock phase adjustment mechanism as an intermediary between the clock signal source and the source/sink circuits. This intermediary component dynamically modifies the clock phase shift amount based on operating frequency detection. By placing this phase adjustment intermediary in the clock distribution path, the system can maintain constant propagation delay margin without requiring complex redesign of the entire clock distribution network for different operating modes.
Data Source
AI summary
Provided is a register clock driver including an input node configured to receive an input signal from a memory controller, an output node configured to output an output signal to a memory device, and an operating circuit configured to buffer the input signal and including a source circuit, a combination logic circuit, and a sink circuit, the source circuit including source flip-flop, and the sink circuit including sink flip-flops. The source circuit is configured to receive a first clock signal, and the sink circuit is configured to receive a second clock signal different from the first clock signal, and the second clock signal is a clock signal delayed by a clock delay from the first clock signal, and the clock delay is determined based on a propagation delay margin.