Register File Read Port Sharing for Three-Operand Instructions

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Solution Overview

Problem

Conventional register file hardware faces increased time delay, power consumption, and area requirements when supporting three-operand instructions, as it typically requires additional dedicated read ports, which negatively impacts performance and the number of rename registers that can be supported.

Innovation Solution

A central processing unit with a register file having multiple read ports and logic to selectively couple these read ports to input ports of an execution unit, allowing for staggered read operations based on the type of instruction, thereby optimizing the use of existing ports for three-operand instructions without the need for additional dedicated ports.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a third dedicated read port is added to support three-operand instructions, then the instruction support capability is improved, but the time delay, power consumption, and area increase

Engineering Contradiction:

Improveinstruction support capabilityVSAvoidregister file read delay

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements dynamic port sharing where the register file read ports are selectively assigned to different execution units based on the instruction type. For three-operand instructions, ports are shared between execution units in a time-multiplexed manner, allowing the system to adapt port allocation dynamically rather than requiring dedicated ports for each instruction type

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The read ports are designed to serve multiple functions by being shared between different execution units (first and second execution units) depending on the instruction being executed. This multi-functional port design allows a single port to support both two-operand and three-operand instructions, eliminating the need for dedicated ports for each case

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If a third dedicated read port is added to support three-operand instructions, then the instruction support capability is improved, but the power consumption increases

Engineering Contradiction:

Improveinstruction support capabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the port allocation responsibilities by having execution units share common read ports through time-multiplexed access. Instead of having separate dedicated ports for each execution unit, the system combines port usage into a shared resource, reducing the total number of physical ports and consequently the power consumption while maintaining support for three-operand instructions

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If a third dedicated read port is added to support three-operand instructions, then the instruction support capability is improved, but the area required increases

Engineering Contradiction:

Improveinstruction support capabilityVSAvoidregister file area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The read ports are designed to serve multiple functions by being shared between different execution units depending on the instruction being executed. This multi-functional port design allows a single port to support both two-operand and three-operand instructions, eliminating the need for dedicated ports for each case and thereby reducing the overall area required

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If additional dedicated read ports are added, then three-operand instructions are supported, but the number of rename registers that can be supported decreases

Engineering Contradiction:

Improveinstruction support capabilityVSAvoidnumber of rename registers

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The system dynamically allocates read ports based on the instruction being executed, allowing the maximum number of rename registers to be supported. By using time-multiplexed port sharing for three-operand instructions, the architecture maintains flexibility in register renaming while still supporting the required instruction types, rather than being constrained by fixed dedicated port allocations

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9430237B2Sharing register file read ports for multiple operand instructions

Publication Date: 2016.08.30 ADVANCED MICRO DEVICES INC

AI summary

A central processing unit includes a register file having a plurality of read ports, a first execution unit having a first plurality of input ports, and logic operable to selectively couple different arrangements of the read ports to the input ports. A method for reading operands from a register file having a plurality of read ports by a first execution unit having a first plurality of input ports includes scheduling an instruction for execution by the first execution unit and selectively coupling a particular arrangement of the read ports to the input ports based on a type of the instruction.