Register Circuit Level Shifting for Low-Voltage Clock Reliability
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Solution Overview
Problem
Conventional latch and register circuits face difficulties in reliably registering data using lower voltage clocks, particularly in low power operating states of microprocessors, where clock skew disparities and insufficient time for level-shifting core data signals pose challenges.
Innovation Solution
A register circuit comprising a level shift circuit, a latch isolation circuit, and a keeper circuit, implemented with P-channel and N-channel devices, that toggles between reference and upper voltage levels to effectively register data using a lower voltage clock, ensuring proper data state registration even during reduced voltage conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If lower voltage clocks are used during low power states, then power consumption is reduced, but data registration reliability deteriorates
Solution Approach 1:
The patent introduces intermediate voltage levels (upper voltage level between reference and full voltage) and intermediate circuits (level shift circuit, keeper circuit) to enable reliable data registration at reduced clock voltages. The level shift circuit translates between different voltage domains, while the keeper circuit maintains stable output states during low voltage operation, thus resolving the reliability issue without requiring full voltage clocks.
Solution Approach 2:
The patent changes the voltage parameter of the clock signal from full voltage to reduced voltage levels while introducing compensating mechanisms. By operating the clock at lower voltage levels and compensating with level shift and keeper circuits, the system achieves power reduction while maintaining functional reliability.
2Speed
If higher voltage clock signals are used across the chip die, then data registration speed is improved, but clock skew disparities increase
Solution Approach 1:
The patent applies different voltage levels to different regions or functions on the chip die. Core logic operates at reduced voltage levels while maintaining proper clock skew relationships, whereas specific interfaces or islands may operate at higher voltage levels as needed. This localized voltage differentiation allows speed optimization in specific areas without causing global clock skew problems.
3Adaptability or versatility
If conventional level-shift circuits are used for frequency disparity, then voltage level translation is achieved, but sufficient time for level-shifting is not available
Solution Approach 1:
The patent prepares voltage level translation in advance by using the level shift circuit to pre-translate signals before they need to be used. The keeper circuit also pre-establishes stable output states before clock edges arrive, ensuring that when high-speed operation is required, the signals are already prepared and no additional level-shifting time is needed during critical timing windows.
Data Source
AI summary
A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage level in response to a clock node and an input node. The clock node toggles between the reference voltage level and a lower voltage level. The latch isolation circuit isolates an output node from the input node when the clock node is at the reference voltage level, and asserts the output node to one of the reference voltage level and an upper voltage level based on a state of the input node when the clock node is at the lower voltage level. The keeper circuit maintains a state of the output node when the clock node is at the reference voltage level.