Register Mapping via State-Based Pool Allocation
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Solution Overview
Problem
Conventional register mapping technologies face performance degradation due to the need for shifting register content between operating systems and hypervisors, and are limited by the number of supported registers, leading to increased cost and power consumption in multi-threading environments.
Innovation Solution
A register mapping technique that utilizes a register pool and a mapping table with operational state parameters to efficiently manage register access across multiple operating systems and hardware threads, allowing for dynamic allocation and access based on operational states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional register mapping technology provides one register for hypervisor and another for OS, then register access performance is improved, but the number of supported registers is limited requiring memory evacuation for unsupported registers
Solution Approach 1:
The invention divides the register management into segments: a register pool containing multiple registers is created, and a mapping table is segmented into multiple entries where each entry corresponds to a specific register. This segmentation allows different registers to be mapped to different hardware threads based on operational state, enabling support for more registers without memory evacuation.
Solution Approach 2:
The mapping table serves as a universal mechanism that can map any register from the register pool to any hardware thread based on the current operational state. This multi-functional approach allows the same mapping table structure to handle different register allocation scenarios (hypervisor mode, different OS modes, different thread states) without requiring separate dedicated registers for each case.
2Adaptability or versatility
If multiple hardware threads operate on a single processor core with classified registers, then virtualization functionality is improved, but register switching between threads degrades performance
Solution Approach 1:
The mapping table is pre-configured with multiple entries that define the register mapping for different operational states (hypervisor mode, different OS modes, different thread states) before switching occurs. When a hardware thread needs to switch states, the system can quickly retrieve the pre-configured mapping from the mapping table without performing complex real-time analysis, thereby reducing register switching overhead.
3Productivity
If a register pool with mapping table is implemented, then register access performance is improved by eliminating memory evacuation, but device complexity increases
Solution Approach 1:
The mapping table is designed to be self-descriptive, with each entry containing all necessary information (register identifier, operational state parameters) to perform mapping decisions. The system uses the mapping table itself to determine the correct mapping without requiring external control logic or complex decision-making processes, thereby reducing overall system complexity despite the added structure.
Data Source
AI summary
A technique for register mapping in a virtual system includes preparing a register pool that includes a plurality of registers for mapping. A mapping table is prepared that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers. At the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation is acquired. One of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, is set as a mapped register to be accessed per the register access request.