Register Retiming Critical Chain Detection for Timing Closure
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Solution Overview
Problem
Conventional timing closure methods in electronic design automation (EDA) tools for complex systems like FPGAs and ASICs face challenges in optimizing critical paths due to the complexity of register retiming, which often transforms the problem from local to global, requiring a new level of abstraction beyond the study of critical paths.
Innovation Solution
The method involves detecting and reporting critical chains with multiple register-to-register paths, where improving timing on one path improves timing on others, by generating directed graphs to identify dependencies and constraints, and modifying the system based on these chains to optimize timing closure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If register retiming is performed to optimize timing closure, then timing performance is improved, but the problem transforms from local to global requiring higher abstraction
Solution Approach 1:
The patent introduces a new dimension of analysis by creating critical chains that connect multiple register-to-register paths across different clock domains. This transforms the local timing analysis into a global view by adding the dimension of chain-level dependencies, where improving timing on one path automatically improves timing on related paths within the same critical chain.
2Ease of manufacture
If conventional critical path analysis is used, then local timing optimization is achieved, but global timing interactions are missed
Solution Approach 1:
The patent merges multiple related register-to-register paths into a single critical chain structure. By combining paths that share common timing constraints and dependencies, the analysis captures global timing interactions while maintaining the detail needed for local optimization. This merging preserves timing relationship information that would be lost in isolated path analysis.
3Reliability
If multiple timing constraints and asynchronous conditions are addressed in register retiming, then timing closure is achieved, but the number of constraints and complexity increases
Solution Approach 1:
The patent segments the complex timing analysis problem into manageable critical chains, each representing a specific group of related paths with shared constraints. By dividing the global timing problem into discrete chain segments, the tool can systematically handle multiple timing constraints and asynchronous conditions without overwhelming complexity, making the constraint management more tractable.
Data Source
AI summary
A method for designing a system on a target device includes performing register retiming on the system. A critical chain in the system is detected, wherein the critical chain includes a plurality of register-to-register paths and where improving timing on one of the register-to-register paths improves timing on other register-to-register paths. Properties of the critical chain are reported.