Register Verification Circuit Using Complementary Bits
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Solution Overview
Problem
Existing electronic devices face challenges in ensuring the reliability and accuracy of data stored in registers, particularly due to potential modifications caused by cosmic radiation, which can compromise user safety.
Innovation Solution
The implementation of a device with at least two registers, each containing a data word and a verification bit, where the verification bit is obtained by applying a function to the data word, and a common binary word is used to determine the value of the verification bits, allowing for cyclic verification of register contents using XOR-type functions and inverters to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification bits are added to each register to detect errors, then data reliability is improved, but device complexity increases
Solution Approach 1:
The verification bit is calculated and stored in advance along with the data word in the register. This preliminary action allows error detection to occur automatically during normal operations without requiring additional real-time computation, thus improving reliability while minimizing the increase in device complexity.
Solution Approach 2:
A dedicated verification circuit acts as an intermediary component that separately handles the verification bit calculation and comparison operations. This mediator approach isolates the error detection functionality from the main data processing path, allowing reliability improvement through specialized verification logic while keeping the overall device architecture organized and manageable.
2Reliability
If multiple registers are used for verification, then error detection capability is improved, but loss of time increases
Solution Approach 1:
The verification process operates continuously in the background without interrupting the normal data flow. The verification circuit continuously monitors the verification bits alongside data operations, ensuring that error detection capability is maintained at all times without causing time loss or operational delays.
Solution Approach 2:
Multiple registers are pre-configured with their verification bits during system initialization or data loading. This preliminary setup allows the verification process to begin immediately without requiring sequential computation, thereby improving error detection capability while minimizing verification time.
3Measurement precision
If verification bits are stored in each register, then data accuracy is improved, but manufacturing complexity increases
Solution Approach 1:
The verification bits are automatically generated and stored in the registers during the manufacturing or data loading process. This preliminary action integrates the verification mechanism into the existing data storage workflow, improving data accuracy while avoiding the need for separate manual configuration steps that would increase manufacturing complexity.
Solution Approach 2:
Each register is designed to self-generate its verification bit through an integrated verification circuit that automatically calculates and stores the verification bit alongside the data word. This self-service approach eliminates the need for external intervention or complex manual setup during manufacturing, thereby improving data accuracy without significantly increasing manufacturing complexity.
Data Source
AI summary
In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.