Reinforcement Layer Frame for Electronic Component Connection
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Solution Overview
Problem
Electronic components in circuit arrangements experience mechanical and thermomechanical stresses due to differing expansion coefficients, leading to 'clam-shell marked fractures' and reduced service life, especially under temperature fluctuations, and existing stress reduction methods like metal oxide coatings are costly and difficult to apply.
Innovation Solution
A connection arrangement with a reinforcement layer having a higher modulus of elasticity than the connection layer, configured in a frame-like manner to absorb and prevent deformation, which can be formed from intermetallic phases and conventional connection materials, effectively protecting the component from crack initiation and expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal oxide coating is applied to the entire arrangement to reduce stress, then stress reduction for the semiconductor chip is achieved, but the manufacturing cost increases and the application process becomes difficult and expensive
Solution Approach 1:
The patent applies stress reduction functionality locally rather than globally. The reinforcement layer is positioned specifically at the edges of the semiconductor chip where stress concentration occurs, rather than coating the entire arrangement. This localized approach reduces manufacturing complexity and cost while maintaining effective stress reduction where it is most needed.
Solution Approach 2:
The solution segments the stress reduction function into a separate reinforcement layer component that is distinct from the semiconductor chip and its coating. This reinforcement layer is applied only to specific regions (edges) rather than requiring a complete coating of the entire assembly, thereby simplifying the manufacturing process.
2Reliability
If dimples are introduced into the substrate surface to reduce mechanical stresses, then the substrate becomes more elastic and stress breakdown is achieved, but an additional manufacturing step is required
Solution Approach 1:
Instead of modifying the entire substrate surface with dimples, the patent applies a reinforcement layer locally at the chip edges where stress concentration occurs. This avoids the need for additional substrate processing steps while achieving the same stress reduction effect in the critical regions.
3Reliability
If the reinforcement layer is formed in a frame-like manner enclosing the connection face, then crack formation is prevented through suppressed expansion, but the structural complexity increases
Solution Approach 1:
The reinforcement layer is configured as a frame-like structure only at the periphery of the semiconductor chip where stress concentration and crack initiation are most likely to occur. This localized framing approach provides effective crack prevention without requiring a complete structural modification of the entire chip assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents crack formation and expansion in electronic components, ensuring reliability and longevity under temperature fluctuations, using conventional materials and methods, and allowing for easy manufacturing and handling.
Implementation Method 1
The reinforcement layer has a higher modulus of elasticity than the connection layer. In so doing, a crack formation in the connection layer can advantageously be prevented, which occurs in otherwise known connection arrangements as a result of mechanical and/or thermomechanical stresses
Implementation Method 2
The at least one electric and/or electronic component has at least one connection face, which is connected in a bonded manner to a join partner by means of a connection layer. The connection layer can, for example, be an adhesive, soldered, welded, sintered connection
Implementation Method 3
Due to the difference between ambient, joining and operating temperature, the rigidity of the connection layer and the distinctly different expansion coefficients of, for example, IC and substrate, very high mechanical or thermomechanical stresses can however occur in the electronic components
Data Source
AI summary
The connection arrangement (100, 200, 300, 400) comprises at least one electric and/or electronic component (1). The at least one electric and/or electronic component (10) has at least one connection face (11), which is connected in a bonded manner to a join partner (40) by means of a connection layer (20). The connection layer (20) can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer (30′) is arranged adjacent to the connection layer (20) in a bonded manner. The reinforcement layer (30′) has a higher modulus of elasticity than the connection layer (20). A particularly good protective effect is achieved if the reinforcement layer (30′) is formed in a frame-like manner by an outer and an inner boundary (36, 35) and, at least with the outer boundary (36) thereof, encloses the connection face (11) of the at least one electric and/or electronic component (10).