Related Clock Domains Using a Common Base Clock Network
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Solution Overview
Problem
Modern integrated circuits face challenges in synchronously communicating between clock domains due to appreciable clock skew, which limits the predictability of timing relationships and the clock rates that can be operated, especially when using phase lock loops or clock dividers.
Innovation Solution
The implementation of an integrated circuit with multiple clock domains operating at user-specified data rates, where the data rates are controlled by a modulating signal and reconfigurable circuits, allowing for precise control of clock frequencies and phase relationships through the modulation of counter enable signals and reconfiguration states, effectively creating synchronously related clocks within a common base clock distribution network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase lock loops or clock dividers are used to create related clocks, then synchronous communication between clock domains is enabled, but appreciable clock skew occurs which limits timing predictability and operational clock rates
Solution Approach 1:
The patent merges multiple clock domains into a single unified clock distribution network, where all clock domains share a common base clock. This eliminates the need for separate PLLs or clock dividers that cause skew, allowing synchronous communication while maintaining precise timing relationships through the unified network.
Solution Approach 2:
The unified clock distribution network serves multiple functions simultaneously: it provides clock signals to multiple clock domains, enables synchronous communication, and maintains precise timing relationships. This single universal system replaces the need for multiple specialized clock generation components.
2Adaptability or versatility
If separate PLLs are used for different clock domains, then each domain can operate at unique clock frequencies, but the device complexity increases and clock skew occurs
Solution Approach 1:
The unified clock distribution network provides multiple clock frequencies to different domains through a single system, enabling frequency adaptability without requiring separate PLLs for each domain. This universal approach reduces device complexity while maintaining the ability to operate at unique frequencies.
Solution Approach 2:
The system changes clock frequency parameters within the unified distribution network by adjusting division ratios or frequency multiplication factors, allowing different clock domains to operate at unique frequencies without adding complex hardware components.
3Adaptability or versatility
If asynchronous interface is used for signal transfer between clock domains, then no clock relationship is required, but specialized circuitry is needed that cannot be easily verified
Solution Approach 1:
The patent replaces complex asynchronous interface circuitry with simpler synchronous interface mechanisms that leverage the unified clock network. The simplified circuitry is easier to verify and implement, effectively replacing expensive/complex asynchronous components with more affordable/simple synchronous alternatives.
4Ease of manufacture
If clocks from different distribution networks are used, then each domain can be independently optimized, but clock skew between domains becomes appreciable
Solution Approach 1:
The patent combines multiple independent clock distribution networks into a single unified network, maintaining the ability to independently configure each clock domain while eliminating inter-domain clock skew. The unified network ensures synchronized timing across all domains through shared base clock distribution.
Data Source
AI summary
An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.