Relaxation Oscillator Circuit With Isolated Parasitic Capacitance
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Solution Overview
Problem
Existing relaxation oscillating circuits face issues with poor output signal accuracy and temperature stability due to parasitic capacitors affecting oscillation frequency, especially in constant current mode where parasitic capacitors are introduced into the oscillating loop.
Innovation Solution
A relaxation oscillating circuit design that isolates parasitic capacitors using isolating transistors in the charging and discharging circuits, with auxiliary and main transistors arranged in mirror configurations to control the clock signal and control signal timing, reducing the influence of drain capacitors on the charging-discharging capacitor, and utilizing a bias circuit for temperature-independent charging-discharging current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a switched resistor is used in the oscillating loop to change oscillation frequency, then frequency adjustment is achieved, but parasitism increases causing poor output signal accuracy and temperature stability
Solution Approach 1:
The patent extracts the parasitic elements (switched resistor and its parasitic capacitor) from the oscillating loop by introducing an isolating transistor. The switched resistor is placed outside the loop and coupled through the isolating transistor, which blocks the parasitic capacitor from affecting the loop's oscillation frequency, thus resolving the contradiction between frequency adjustment capability and output signal accuracy
Solution Approach 2:
The isolating transistor acts as an intermediary between the switched resistor and the oscillating loop. It allows the switched resistor to control the oscillation frequency while preventing its parasitic capacitor from directly affecting the loop, thereby maintaining both frequency adjustability and signal accuracy
2Reliability
If a current transistor mode is used to change oscillation frequency, then the switch is outside the oscillating loop avoiding switch resistance influence, but parasitic capacitor of the current transistor affects accuracy and temperature stability especially at high frequencies
Solution Approach 1:
The patent extracts the parasitic capacitor of the current transistor from the oscillating loop by introducing an isolating transistor. The current transistor remains outside the loop while being coupled through the isolating transistor, which prevents the parasitic capacitor from affecting the loop's oscillation, thus resolving the contradiction between avoiding switch resistance influence and maintaining signal accuracy
Solution Approach 2:
The isolating transistor serves as an intermediary that allows the current transistor to control oscillation frequency while blocking its parasitic capacitor from affecting the oscillating loop, thereby maintaining both the advantage of switch being outside the loop and the accuracy required for high-frequency operation
3Device complexity
If parasitic capacitors are introduced into the oscillating loop, then circuit implementation is simplified, but temperature stability deteriorates
Solution Approach 1:
The patent extracts parasitic capacitors from the oscillating loop by using an isolating transistor to couple external resistors to the loop. This allows the use of simple RC circuits for frequency adjustment while preventing parasitic capacitors from entering the loop, thus achieving both simplified implementation and temperature stability
Solution Approach 2:
The isolating transistor acts as an intermediary that enables simple RC frequency adjustment circuits to be used while blocking parasitic capacitors from affecting the oscillating loop, thereby maintaining temperature stability without increasing circuit complexity
Data Source
AI summary
Provided is a relaxation oscillating circuit, which comprises a charging circuit, a discharging circuit, a switch circuit, a charging-discharging capacitor and an output circuit. The charging circuit comprises a first current source and a first isolating transistor. The discharging circuit comprises a second current source and a second isolating transistor. The switch circuit comprises a main charging transistor and an auxiliary charging transistor arranged as mirror and a main discharging transistor and an auxiliary discharging transistor arranged as mirror. The main charging transistor and the main discharging transistor are alternately conducted. According to a voltage of the charging-discharging capacitor, the output circuit outputs a clock signal and a control signal. The clock signal is connected to control ends of the auxiliary charging transistor and the auxiliary discharging transistor, and the control signal is connected to control ends of the main charging transistor and the main discharging transistor.