Replacement Gate CMOS Epitaxy Without Contact Opening Masks
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in selectively forming source/drain epitaxial layers at low thermal budgets, particularly in CMOS technology, where introducing dopants can make selective epitaxial growth non-selective, and existing methods are not suitable for nm-scale structures using Ge or SiGe, and require additional masks like contact opening masks in replacement gate technology.
Innovation Solution
A novel replacement gate technology that eliminates the need for a contact opening mask and employs a non-selective source/drain epitaxial process, allowing for epitaxial layer formation at temperatures below 500°C, using SiP and SiGe materials, with a height difference of less than 5 nm between the epitaxial layer and the gate electrode, and forming the source/drain epitaxial layer laterally beyond the source and drain regions on a dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dopants are introduced to form source/drain regions, then electrical conductivity is improved, but selective epitaxial growth becomes non-selective
Solution Approach 1:
The patent performs preliminary doping of the semiconductor layer before epitaxial growth, rather than introducing dopants during the epitaxial process. This preliminary doping action establishes the electrical conductivity needed for source/drain regions while preserving the selectivity of subsequent epitaxial growth, as the doping occurs in a separate preparatory step that does not interfere with the epitaxial process selectivity
Solution Approach 2:
The patent segments the source/drain formation process into distinct stages: preliminary doping of the semiconductor layer, selective epitaxial growth of the source/drain layers, and subsequent processing. This segmentation allows each step to be optimized independently - the doping step ensures electrical conductivity while the epitaxial growth step maintains selectivity, resolving the contradiction between these two requirements
2Length of moving object
If replacement gate technology is used, then gate length is reduced, but additional masks like contact opening masks are required
Solution Approach 1:
The patent merges the contact hole formation and gate electrode formation steps into a single lithography and etching process. By using the same mask pattern for both contact holes and gate electrodes, and performing both etching operations sequentially without requiring an additional contact opening mask, the method achieves reduced gate length while avoiding the increased device complexity of multiple masks
Solution Approach 2:
The patent creates a universal mask pattern that serves multiple functions - defining both contact holes and gate electrodes in a single lithography step. This multi-functional approach eliminates the need for separate contact opening masks, reducing the overall number of masking steps while maintaining the ability to achieve reduced gate lengths through the replacement gate methodology
3Temperature
If selective epitaxial growth is performed at low thermal budget, then existing structures are preserved, but dopant introduction makes growth non-selective
Solution Approach 1:
The patent performs preliminary doping of the semiconductor layer before the low-temperature epitaxial growth process. By establishing the dopant distribution in advance at lower temperatures, the subsequent epitaxial growth can proceed selectively at low thermal budget without the dopant introduction interfering with growth selectivity, as the doping and epitaxial growth are decoupled into separate sequential steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and selective source/drain epitaxial growth without increasing the number of lithography processes, reducing gate length, and allowing for larger contact areas, making it suitable for back-end-of-line processes in semiconductor manufacturing.
Implementation Method 1
a source/drain epitaxial layer is formed over the source and drain regions
Data Source
AI summary
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.