Replacement Gate Etching Cycles for High-Aspect-Ratio Gate Structures
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Solution Overview
Problem
The increasing aspect ratio of sacrificial gate structures in semiconductor manufacturing poses challenges in filling gate electrode layers during the replacement gate process, particularly near high-k dielectric features, leading to issues like over or under etching and reduced volume of source/drain regions, which affects device performance.
Innovation Solution
A cyclic etching and passivation process is employed to form sacrificial gate structures, involving bulk etching followed by cyclic fine etching with alternating passivation and pumping out stages, to prevent over or under etching near high-k dielectric features, ensuring consistent gate structure dimensions and volume of source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but the aspect ratio of sacrificial gate structures increases making it difficult to fill gate electrode layer
Solution Approach 1:
The etching process is segmented into multiple cycles with alternating etching and passivation steps, allowing precise control of the sacrificial gate structure dimensions while maintaining the ability to fill gate electrode layers in high aspect ratio spaces
Solution Approach 2:
The patent employs periodic cyclic etching and passivation actions to progressively shape the sacrificial gate structures, enabling precise dimensional control that facilitates subsequent gate electrode layer filling in high aspect ratio regions
2Quantity of substance
If aspect ratio of sacrificial gate structures increases, then integration density improves, but etching control near high-k dielectric features deteriorates causing over or under etching
Solution Approach 1:
The cyclic etching and passivation process applies periodic actions that allow the etch front to progress controllably through the sacrificial gate material, with passivation steps preventing over-etching near high-k dielectric features and ensuring consistent dimensions
Solution Approach 2:
The cyclic process provides inherent feedback control where each etching step is followed by passivation, allowing real-time adjustment of etching depth and preventing both over-etching and under-etching near sensitive high-k dielectric regions
3Quantity of substance
If aspect ratio of sacrificial gate structures increases, then integration density improves, but volume of source/drain regions is reduced affecting device performance
Solution Approach 1:
The segmented cyclic etching process enables precise control of sacrificial gate dimensions, allowing optimization of the balance between gate structure aspect ratio and source/drain region volume to maintain device performance while achieving high integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method maintains precise gate structure dimensions and source/drain regions, enhancing device performance by preventing defects and improving yield in semiconductor manufacturing.
Implementation Method 1
performing an etching process
Implementation Method 2
performing a passivation process
Data Source
AI summary
A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.