Replacement Gate Isolation Between Fins for Residue-Free Fill
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration of transistors and other components becomes more challenging due to issues with residue removal and filling efficiency in the formation of gate isolation regions, leading to potential voltage threshold shifts and reduced device performance.
Innovation Solution
The formation of gate isolation regions with a tapered profile, achieved by etching recesses between neighboring fins and depositing sacrificial material on their sidewalls, allows for more complete residue removal and improved filling efficiency during subsequent process steps by controlling the shape and size of these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate isolation region formation is used, then manufacturing process is simpler, but residue removal is incomplete and filling efficiency is reduced
Solution Approach 1:
The method performs preliminary actions by forming a tapered profile in the gate isolation region before filling it with metal. The tapering process creates a specific geometry (narrower at the top, wider at the bottom) that预先 prepares the structure for complete residue removal and efficient metal filling, addressing the residue removal problem before the actual filling occurs.
Solution Approach 2:
The gate isolation region is given an asymmetric tapered profile where the top width is intentionally made smaller than the bottom width. This asymmetric geometry is specifically designed to facilitate complete residue removal from the top while maintaining adequate space at the bottom for stable metal filling, directly resolving the contradiction between residue removal completeness and filling efficiency.
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but voltage threshold shifts and device performance degrade
Solution Approach 1:
The method applies local quality by creating a non-uniform tapered profile specifically in the gate isolation region, where the top and bottom have different widths. This localized geometric modification targets the specific area causing voltage threshold shifts, allowing the rest of the device to maintain its scaled dimensions for high integration density while this specific region provides the stability needed for reliable voltage thresholds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of semiconductor devices by ensuring complete residue removal and efficient metal fill, reducing undesirable voltage shifts and improving processing consistency.
Implementation Method 1
etching the dummy gate through the opening in the patterned mask to form a recess in the dummy gate, the etching including a plasma etching process
Implementation Method 2
the plasma etching process using process gases including one or more etching gases and one or more polymer-forming gases, wherein during the etching the process gases react with the material of the dummy gate to form reaction products that deposit on sidewalls of the recess
Implementation Method 3
depositing an insulation material to fill the recess
Data Source
AI summary
A method includes forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; etching the dummy gate material using a first etching process to form a recess between the first fin and the second fin, wherein a sacrificial material is formed on sidewalls of the recess during the first etching process; filling the recess with an insulation material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate over the first fin and a second replacement gate over the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulation material.