Gate All Around Nanowire FET Replacement Gate Fin First Process
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Solution Overview
Problem
Fabricating gate all around nanowire field effect transistors (FETs) is challenging due to difficulties in forming gates surrounding nanowires at scaled dimensions, which hinders layout density scaling and increases parasitic capacitance.
Innovation Solution
A replacement gate fin first, wire last process is employed, involving the formation of sacrificial layers, patterned fins, dummy gates, gap filler material deposition, and removal of dummy gates to create trenches for forming replacement gates that surround nanowire channels in a gate all around configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanowires are placed close together and/or stacked to increase layout density, then layout density is improved, but forming a gate surrounding the nanowires becomes challenging
Solution Approach 1:
The patent applies preliminary action by forming dummy gates before releasing the nanowires from the sacrificial fin structure. The dummy gates are formed while the nanowires are still constrained within the fin, making subsequent gate-all-around formation easier. After the dummy gates are in place, the sacrificial layer is removed to release the nanowires, and the dummy gates are replaced with functional gates that fully surround the nanowires.
Solution Approach 2:
The patent uses dummy gates as an intermediary structure to facilitate the formation of gate-all-around devices. The dummy gates serve as placeholders that enable precise positioning and alignment during fabrication, and are later replaced with the final functional gates. This intermediary step simplifies the overall manufacturing process by breaking it into manageable stages.
2Object-generated harmful factors
If conventional fabrication techniques are used, then manufacturing simplicity is maintained, but parasitic capacitance increases and layout density scaling is hindered
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming sacrificial fin structures with embedded nanowires, forming dummy gates, releasing the nanowires by removing sacrificial layers, and forming replacement gates. This segmentation allows each step to be optimized independently, achieving gate-all-around configuration that minimizes parasitic capacitance while managing fabrication complexity through systematic process breakdown.
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures by forming gates that surround the nanowire channels on all sides. This dimensional change from 2D to 3D gate configuration improves electrostatic control and reduces parasitic capacitance, while the use of dummy gates and sacrificial structures enables this complex 3D formation through adapted 2D fabrication techniques.
Data Source
AI summary
In one aspect, a method of fabricating a nanowire FET device includes the following steps. A wafer is provided. At least one sacrificial layer and silicon layer are formed on the wafer in a stack. Fins are patterned in the stack. Dummy gates are formed over portions of the fins which will serve as channel regions, and wherein one or more portions of the fins which remain exposed will serve as source and drain regions. A gap filler material is deposited surrounding the dummy gates and planarized. The dummy gates are removed forming trenches in the gap filler material. Portions of the silicon layer (which will serve as nanowire channels) are released from the fins within the trenches. Replacement gates are formed within the trenches that surround the nanowire channels in a gate all around configuration. A nanowire FET device is also provided.