Replacement Gate Spacer Structure for Nanostructure Shape Control
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in controlling the shape and dimensions of nanostructures, which affect the electrical properties and uniformity of semiconductor devices.
Innovation Solution
By controlling the atomic concentration of elements like Ge in semiconductor compounds of sacrificial layers, the shape and dimensions of replacement gate and inner spacer structures are manipulated to improve the electrical properties and uniformity of nanostructure devices, while also enhancing etching resistance and reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but controlling the shape and dimensions of nanostructures becomes more difficult
Solution Approach 1:
The patent applies parameter changes by varying the atomic concentration of germanium in sacrificial layers to control the etching rates during nanostructure formation. By adjusting compositional parameters of the sacrificial layers, the patent achieves precise control over the shape and dimensions of replacement gate structures and channel regions, resolving the contradiction between reduced feature size and manufacturing precision
Solution Approach 2:
The patent implements local quality by creating sacrificial layers with different germanium atomic concentrations at different locations and depths. This allows different regions of the nanostructure to be formed with specific dimensional characteristics, enabling precise control over channel length and gate structure geometry while maintaining high integration density
2Reliability
If replacement gate structures are used to improve electrical properties, then device performance is enhanced, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent applies preliminary action by forming sacrificial layers with controlled germanium concentrations before the main device fabrication steps. These pre-formed sacrificial structures guide subsequent etching and material deposition processes, enabling the creation of replacement gate structures with desired electrical properties while streamlining the overall manufacturing sequence
Solution Approach 2:
The patent uses parameter changes in the sacrificial layer composition (germanium atomic concentration) to control the etching selectivity and rate. This allows the replacement gate structures to be formed with precise dimensional control, achieving improved electrical properties through a controlled, systematic process rather than complex trial-and-error fabrication
Data Source
AI summary
An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.