Replacement Gate Stack Reducing CMOS Gate Resistance
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Solution Overview
Problem
Existing replacement metal gate (RMG) processing techniques face challenges in reducing the total gate resistance of p-type and n-type field-effect transistors (FETs) without affecting the work function of the gate stack metals in CMOS integrated circuits.
Innovation Solution
A method involving the formation of interfacial and high-k layers, followed by specific work function metal layers and gate electrode layers in distinct openings for pFET and nFET regions, allowing for the creation of replacement gate stacks that reduce gate resistance while maintaining the work function of the gate stack metals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replacement metal gate (RMG) processing is used to reduce gate resistance, then gate resistance decreases, but work function of the gate stack metals is affected
Solution Approach 1:
The patent applies local quality by forming different work function metal layers for pFET and nFET regions. Specifically, a first work function metal layer is formed in the first opening over the pFET region, and a second work function metal layer is formed in the second opening over the nFET region. This allows each transistor type to have optimized local electrical properties while using a common gate electrode layer, thereby reducing gate resistance without compromising the specific work function requirements of each device type.
Solution Approach 2:
The gate structure is segmented into distinct functional layers: an interfacial layer, a high-k dielectric layer, work function metal layers (with different materials for pFET and nFET), and a common gate electrode layer. This segmentation allows independent optimization of each layer's properties - the high-k layer provides gate control, while the separate work function metal layers enable precise tuning of threshold voltages for different transistor types without affecting overall gate resistance.
2Manufacturing precision
If different work function metal layers are formed for pFET and nFET, then work function is maintained, but device complexity increases
Solution Approach 1:
The patent merges the common elements of the gate stack - specifically, a single gate electrode layer is formed over both the first work function metal layer (for pFET) and the second work function metal layer (for nFET). This merging approach reduces device complexity by eliminating the need for separate gate electrode formation processes for each transistor type, while still maintaining different work function metal layers to preserve the required work function characteristics for each device type.
Data Source
AI summary
An IC structure including: a first replacement gate stack for the pFET, the first replacement gate stack including: an interfacial layer in a first opening in the dielectric layer; a high-k layer over the interfacial layer in the first opening; a pFET work function metal layer over the high-k layer in the first opening; and a first gate electrode layer over the pFET work function metal layer and substantially filling the first opening; and a second replacement gate stack for the nFET, the second gate stack laterally adjacent to the first gate stack and including: the interfacial layer in a second opening in the dielectric layer; the high-k layer over the interfacial layer in the second opening; a nFET work function metal layer over the high-k layer in the second opening; and a second gate electrode layer over the nFET work function metal layer and substantially filling the second opening.