Replacement Sidewall Spacers for Void-Reduced Gate Cavity Filling
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the reduction in minimum feature size leads to challenges such as the formation of voids and seams in gate cavities during the filling of gate dielectric and electrode layers, resulting in increased gate resistance and performance degradation.
Innovation Solution
The method involves forming a sacrificial gate and sidewall spacers, replacing a portion of the sidewall spacer with a material having a slower etch rate, and widening the gate cavity to facilitate easier filling with reduced voids or seams, ensuring the interlayer dielectric is not etched, and using a replacement spacer structure to control the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate cavity is filled with gate dielectric and electrode layers, then the gate structure is formed, but voids and seams are created resulting in increased gate resistance
Solution Approach 1:
The sidewall spacer is divided into two distinct portions: a first portion with a first etch rate and a second portion with a second etch rate that is slower than the first. This segmentation allows differential etching during gate cavity formation, enabling better control over the cavity shape and filling process to reduce voids and seams.
Solution Approach 2:
Different portions of the sidewall spacer are assigned different material properties (etch rates) to serve different functions. The first portion etches faster to define the lower gate cavity region, while the second portion etches slower to define the upper gate cavity region, creating a tapered structure that facilitates better material filling.
2Manufacturing precision
If the gate cavity is widened to facilitate easier filling, then voids and seams are reduced, but the interlayer dielectric may be etched
Solution Approach 1:
The replacement spacer material acts as an intermediary protective layer between the etchant and the interlayer dielectric. This material has an etch rate slower than the sidewall spacer material, allowing the etchant to selectively remove the sidewall spacer while preserving the interlayer dielectric, thus preventing harmful etching.
Solution Approach 2:
The etch rate parameter is changed by using different materials for different portions of the spacer structure. The second portion uses a material with a slower etch rate, which changes the etching dynamics to widen the gate cavity opening without compromising the interlayer dielectric integrity.
3Object-affected harmful factors
If a replacement spacer structure with slower etch rate is used, then the gate cavity can be widened without etching the interlayer dielectric, but the device complexity increases
Solution Approach 1:
The spacer structure is segmented into two functional portions with different etch rates, allowing selective etching behavior that protects the interlayer dielectric while still enabling gate cavity formation. This segmentation provides a controlled way to manage the etching process without requiring complete redesign of the spacer system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of the gate structure by reducing voids and seams, thereby lowering gate resistance and enhancing manufacturing yields.
Implementation Method 1
the replacement spacer material has a slower etch rate when etched by a selected etchant, as compared to the sidewall spacer material
Data Source
AI summary
Provided is a device with a replacement spacer structure and a method for forming such a structure. The method includes forming an initial spacer structure, wherein the initial spacer structure has an initial etch rate for a selected etchant. The method further includes removing a portion of the initial spacer structure, wherein a remaining portion of the initial spacer structure is not removed. Also, the method includes forming a replacement spacer structure adjacent to the remaining portion of the initial spacer structure to form a combined spacer structure, wherein the combined spacer structure has an intermediate etch rate for the selected etchant that is less than the initial etch rate for a selected etchant. Further, the method includes etching the combined spacer structure with the selected etchant to form a final spacer structure.