Replica Bit-Line Segmentation for SRAM Timing Stability
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Solution Overview
Problem
As memory capacity increases in semiconductor integrated circuits, the fluctuations in the timing of the sense-amplifier enable signal become significant due to increased local delay fluctuations and logic threshold variations, leading to potential read failures in SRAMs using replica bit-lines.
Innovation Solution
The solution involves dividing the replica bit-line into multiple replica bit-lines, each with its own pre-charge transistor and logic circuit, reducing delay fluctuations and logic threshold variations, thereby stabilizing the sense-amplifier enable signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased in semiconductor integrated circuits, then higher memory capacity is achieved, but fluctuations in sense-amplifier enable signal timing increase due to increased local delay fluctuations and logic threshold variations
Solution Approach 1:
The replica bit-line is divided into multiple segments (first replica bit-line and second replica bit-line), each with its own pre-charge transistor and logic circuit. This segmentation reduces the total capacitance on each replica bit-line, thereby reducing delay fluctuations and logic threshold variations that occur when memory capacity increases. The divided structure allows each segment to independently track bit-line delays more accurately, stabilizing the sense-amplifier enable signal timing despite higher memory capacity.
2Reliability
If replica bit-line is divided into multiple replica bit-lines, then delay fluctuations and logic threshold variations are reduced, but device complexity increases due to additional pre-charge transistors and logic circuits
Solution Approach 1:
The replica bit-line is divided into multiple segments (first replica bit-line and second replica bit-line), each with its own pre-charge transistor and logic circuit. This segmentation reduces the total capacitance on each replica bit-line, thereby reducing delay fluctuations and logic threshold variations that occur when memory capacity increases. The divided structure allows each segment to independently track bit-line delays more accurately, stabilizing the sense-amplifier enable signal timing despite higher memory capacity.
Solution Approach 2:
The first and second replica bit-lines are merged through a logic circuit to generate the sense-amplifier enable signal. This merging approach allows the system to benefit from the reduced delay fluctuations of individual segments while combining their outputs to produce a single, stable enable signal, thereby managing complexity through functional integration rather than complete independence of all components.
Data Source
AI summary
Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.