Reprogrammable PUF Memory Block for Stable Updatable Security Keys
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current PUF technologies face challenges in maintaining a stable and reliable unique identity for integrated circuits while also allowing for secure updates in case of security breaches, as existing solutions either rely on permanent keys that are brittle under compromise or revocable keys that are less secure.
Innovation Solution
A reprogrammable physically unclonable function (PUF) structure that utilizes a non-volatile memory device with a memory cell array and security key producing circuitry to generate and update unique identifiers, incorporating a sensing circuit to read and program memory cells based on physical variations, ensuring secure and flexible key management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a permanent key is used for PUF, then the unique identity is stable and reliable, but the key cannot be updated in case of security breaches
Solution Approach 1:
The patent implements a reprogrammable PUF structure where the unique identity can be dynamically updated. The memory cells are designed to allow multiple programming cycles, enabling the PUF to transition from a static permanent key to a dynamic updatable identity. This resolves the contradiction by making the key system adaptable while maintaining reliability through controlled reprogramming capabilities.
Solution Approach 2:
The patent changes the physical state parameters of memory cells through controlled programming and erasing operations. By adjusting voltage parameters and programming conditions, the PUF can regenerate unique identities with different security characteristics. This allows the system to maintain stability through controlled parameter changes while enabling key updates when security breaches occur.
2Adaptability or versatility
If a revocable key is used for PUF, then the key can be updated in case of security breaches, but the security strength is reduced
Solution Approach 1:
The patent implements preliminary hardening actions where the PUF key is programmed and stabilized before actual use. This preliminary programming creates a robust security foundation that maintains strength while allowing future updates. The hardening process prepares the memory cells in advance, ensuring security strength is preserved even as the system gains update capability.
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor the security state and physical characteristics of the PUF. This feedback allows the system to maintain optimal security strength by adjusting programming parameters and detecting potential breaches. The feedback loop ensures that key updates occur only when necessary and are performed in a way that preserves security strength.
3Reliability
If error-correction codes and helper data schemes are employed, then the PUF response stability is improved, but the area and power overhead increase significantly
Solution Approach 1:
The patent extracts and eliminates the need for complex external error-correction codes and helper data schemes by implementing error resilience directly within the PUF structure itself. The memory cell design and programming methodology inherently provide stability without requiring additional external correction mechanisms. This removes the area and power overhead associated with traditional ECC implementations while maintaining response stability.
Solution Approach 2:
The PUF structure is designed to be self-correcting and self-stabilizing through its inherent physical characteristics and programming approach. The memory cells automatically maintain their unique identities without requiring external helper data or complex correction algorithms. This self-service capability reduces device complexity and power consumption while ensuring reliable PUF response stability.
Data Source
AI summary
A non-volatile memory device comprises: a memory cell array with a plurality of non-volatile memory cells; a security key producing circuitry coupled to each column of the memory cell array, the security key producing circuitry configured to perform a series of erase, read, and program operations on a group of the plurality of memory cells to generate a device-specific security key of the memory device, wherein the security key producing circuitry is configured to: erase the group of the memory cells and read erased memory states varied by different physical processing variations of sub-units of each memory cell of the group; and selectively program the sub-units of the erased memory cell based on the erased memory states of the sub-units such that resulting patterns of the programmed states of the erased sub-units are encoded into a permanent, non-volatile digital key.