ReRAM Cell Common Source Configuration for Reset Current Optimization
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Solution Overview
Problem
Conventional ReRAM cell circuits face inefficiencies due to n-type field-effect transistors (NFETs) struggling to drive high currents during reset operations, leading to larger transistor sizes and increased costs.
Innovation Solution
The ReRAM cell is configured to operate in a common source configuration during reset and a source follower configuration during set, with the bit-line connected to the source port and the word-line connected to the gate port, allowing for a lower voltage at the source-line during set and a lower voltage at the bit-line during reset, optimizing NFET size and current supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If NFET is used to drive high current during reset operation, then reset operation is enabled, but transistor size increases and cost increases
Solution Approach 1:
The patent inverts the conventional connection configuration by connecting the bit-line to the source port and the drain port to the resistive element, rather than the conventional approach. This inversion allows the NFET to operate in a common source configuration during reset operations, enabling high current delivery while maintaining smaller transistor size due to improved current drive efficiency
Solution Approach 2:
The patent changes the operating parameters by applying higher voltage to the bit-line during reset operations (e.g., 2.4V) compared to conventional designs, and optimizes the gate voltage to achieve higher overdrive. This parameter change enables the NFET to deliver required high current with smaller device dimensions
2Power
If NFET drives high voltage during reset operation, then reset operation is enabled, but overdrive decreases and body effect increases
Solution Approach 1:
The inverted connection configuration places the NFET in a common source mode during reset operations, where the source is at lower potential and the drain is at higher potential. This configuration improves overdrive voltage and reduces body effect compared to the conventional source follower configuration, enhancing transistor performance reliability at high voltages
Solution Approach 2:
The patent optimizes the local electrical characteristics by creating different voltage conditions at different terminals - the bit-line receives higher voltage (2.4V) during reset while the source-line remains at lower voltage, and the gate voltage is optimized to provide sufficient overdrive. This local quality optimization maintains reliable transistor operation under high voltage conditions
Data Source
AI summary
A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and a resistive element. The FET having a gate port, a drain port, and a source port. The gate port is connected to a word-line (WL) of the ReRAM cell, the source port is connected to a bit-line (BL) of the ReRAM cell, and a first port of the resistive element is connected to the drain of the FET. A second port of the resistive element is connected to a source-line (SL) of the ReRAM cell. During reset operation SL is connected to a high-voltage and BL to a low-voltage. During set operation SL is connected to a low-voltage and BL to a high-voltage. Using this common source configuration overcomes the requirement for a wider FET width of the prior art so as to accommodate the current supply needed during reset operation, and avoids overstressing of the FET.