ReRAM Memory Cell Selector Design for High Density
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Solution Overview
Problem
Conventional memory devices face challenges in achieving high integration density and efficient data storage due to the need for complex lithography processes and the use of MOSFETs in memory cells, which increase costs and reduce operational reliability.
Innovation Solution
A resistive RAM (ReRAM) memory device design that utilizes variable resistance materials and semiconductor layers without MOSFETs, featuring a three-dimensional stacked structure with selectors that include a semiconductor layer and gate insulating films, allowing for higher integration and reduced size of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOSFETs are used in memory cells, then operational reliability is maintained, but integration density is reduced and device size increases
Solution Approach 1:
The patent extracts and eliminates the MOSFET component from the memory cell structure, replacing it with a selector that uses a semiconductor layer and gate insulating films. This removal of the MOSFET reduces the memory cell area while maintaining operational reliability through the alternative selector design.
Solution Approach 2:
The patent changes the fundamental parameters of the memory cell by transitioning from MOSFET-based selection to a semiconductor layer-based selector. This parameter change in the selection mechanism enables smaller cell size while preserving the necessary electrical control functions for reliable operation.
2Manufacturing precision
If complex lithography processes are used, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent segments the fabrication process into simpler stages by using a semiconductor layer and gate insulating films that can be deposited and patterned through less complex lithography processes compared to MOSFET fabrication, thereby reducing overall device complexity while maintaining manufacturing precision.
Solution Approach 2:
The patent employs a semiconductor layer structure that can be fabricated using simpler, more cost-effective lithography processes, replacing the need for complex multi-step MOSFET fabrication. This approach uses more accessible manufacturing techniques to achieve the required precision.
3Ease of operation
If MOSFETs are used in memory cells, then electrical control is achieved, but integration density is reduced
Solution Approach 1:
The patent removes the MOSFET from the memory cell and replaces it with a semiconductor layer-based selector that provides equivalent electrical control functionality in a more compact form, thereby improving integration density while maintaining ease of operation.
Solution Approach 2:
The patent transitions to a three-dimensional stacked structure where the semiconductor layer and gate insulating films are arranged vertically, utilizing the third dimension to achieve compact electrical control without increasing the planar area of the memory cell.
4Ease of manufacture
If conventional memory structures are used, then fabrication is simplified, but integration density and operational reliability are reduced
Solution Approach 1:
The patent changes the structural parameters of the memory cell by adopting a three-dimensional stacked configuration with semiconductor layers and gate insulating films, which simultaneously improves operational reliability and integration density while maintaining fabrication simplicity through established thin-film deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ReRAM design enhances integration density, reduces power consumption, and improves operational reliability by eliminating the need for MOSFETs and minimizing voltage differences between writing, erasing, and reading operations, while also simplifying the fabrication process.
Implementation Method 1
each of memory cells is formed with a non-ohmic element typified by a diode and a variable resistance material
Implementation Method 2
The source region 5, the channel region 6 and the drain region 7 are successively stacked on one of the global bit lines GBL... a gate insulating film 9 is formed on the side surfaces of the channel region 6... a selection gate line 8 is formed in the grooves 45
Data Source
AI summary
According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.