Three-Transistor ReRAM Cell Shared Word Line Leakage Reduction
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Solution Overview
Problem
Conventional ReRAM memory cells require multiple lines for each column and row, leading to increased complexity and leakage issues, especially when using high-voltage transistors, which can be inefficient and costly in terms of area and power consumption.
Innovation Solution
A three-transistor push-pull ReRAM cell configuration using custom low-voltage and high-voltage transistors, with shared p-channel and n-channel word lines, reduces the number of required lines and employs specific voltage potentials for programming and erasing, optimizing the design for lower leakage and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional ReRAM memory cells use multiple lines for each column and row, then the memory array can be formed, but the complexity and leakage issues increase
Solution Approach 1:
The patent combines multiple word lines into shared p-channel and n-channel word lines that serve pairs of adjacent columns. Instead of having separate high-voltage and low-voltage word lines for each column, the invention merges them into shared lines that are selectively activated, reducing the total number of lines while maintaining full memory access capability.
Solution Approach 2:
The shared p-channel word line and shared n-channel word line serve multiple functions: they can individually select either column of a pair, they enable push-pull operation for both columns, and they reduce leakage by keeping unused lines in high-impedance state. This multi-functionality allows the same physical lines to replace what would traditionally require multiple dedicated lines.
2Ease of manufacture
If high-voltage transistors are used in ReRAM cells, then programming and erasing can be performed, but area and power consumption increase
Solution Approach 1:
The patent applies different voltage characteristics to different parts of the memory cell: low-voltage transistors are used for the select switches that require small area, while high-voltage transistors are used only where needed for ReRAM programming. The shared word lines are designed with specific voltage characteristics (p-channel for pull-up, n-channel for pull-down) that enable efficient programming without requiring all transistors to be high-voltage devices.
Solution Approach 2:
The invention changes the voltage parameters dynamically during operation: the shared p-channel word line is activated at specific voltage levels for programming, the shared n-channel word line is activated at complementary voltage levels for erasing, and both lines are held in high-impedance state during non-selection periods. This dynamic parameter change enables full programming capability while minimizing area and power.
3Ease of manufacture
If high-voltage transistors are used in ReRAM cells, then programming and erasing can be performed, but power consumption increases
Solution Approach 1:
The patent employs periodic activation of the shared word lines where only one line is active at a time during selection operations. The p-channel and n-channel word lines are activated in complementary periods: when one is selected for programming, the other is in high-impedance state, and vice versa for erasing. This periodic activation pattern reduces simultaneous power consumption while maintaining full programming and erasing capability.
Solution Approach 2:
The invention converts the potential harm of having unused word lines (which would consume power if always active) into a benefit by placing them in high-impedance state. The shared word line architecture, which could potentially increase complexity, actually reduces power consumption by enabling selective activation and keeping non-selected lines in low-power high-impedance state, thus turning a potential disadvantage into a power-saving feature.
4Area of stationary object
If shared word lines are used between adjacent columns, then area is reduced, but leakage control becomes more challenging
Solution Approach 1:
The patent inverts the traditional approach by using p-channel transistors for the pull-up path and n-channel transistors for the pull-down path in the shared word line configuration. This inversion allows the unused word line to be placed in high-impedance state, effectively blocking leakage paths. The complementary transistor types are strategically positioned to create natural leakage blocking when not in use.
Solution Approach 2:
The shared word lines act as intermediaries that mediate between the bit lines and the ReRAM devices. When one shared word line is active, the other is placed in high-impedance state, serving as an intermediary that blocks leakage current paths. This intermediary high-impedance state effectively isolates the inactive column pair from leakage while maintaining area efficiency through the shared architecture.
Data Source
AI summary
A pair of adjacent ReRAM cells in an array includes a first bit line for a row of the array, a second bit line for the row of the array, a p-channel word line associated with two adjacent columns in the array, and an n-channel word line associated with the two adjacent columns. A pair of ReRAM cells in the adjacent columns in the row each includes a switch node, a first ReRAM device connected between the first bit line and the source of a p-channel transistor. The drain of the p-channel transistor is connected to the switch node, and its gate is connected to the p-channel word line. A second ReRAM device is connected between the second bit line and the source of an n-channel transistor. The drain of the n-channel transistor is connected to the switch node, and its gate is connected to the n-channel word line.