ReRAM Stack Pattern via Selective Deposition

The patent extracts the problematic etching step from the manufacturing process. Instead of using conventional etching to form patterns, the invention directly forms the top electrode and TMO layers in their final patterned shapes through selective deposition, eliminating the etching process that causes interface area loss and switching characteristic deterioration.

The patent applies preliminary action by pre-defining the pattern geometry during the deposition process itself. The top electrode and TMO layers are deposited with precise spatial control from the beginning, so the final pattern and interface area are determined during deposition rather than through subsequent etching, thereby preserving the intended interface area.

The patent changes the deposition parameters and methodology to enable precise control of layer formation at reduced device dimensions. By using selective deposition techniques with controlled deposition rates and spatial distribution, the invention maintains accurate interface area control even when overall device size is reduced for higher integration.

The patent applies local quality by ensuring that the deposition process provides different material distribution characteristics in different spatial locations. The top electrode and TMO layers are deposited with locally optimized properties, maintaining sufficient interface area density even in miniaturized devices, thereby preserving switching characteristics at reduced device sizes.